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freescale semiconductor technical data dsp56321 rev. 11, 2/2005 ? freescale semiconductor, inc., 2001, 2005. all rights reserved. dsp56321 24-bit digital signal processor the freescale dsp56321, a member of the dsp56300 dsp family, supports networking, security encryption, and home entertainment using a high-performance, single-clock-cycle-per- instruction engine (dsp56000 code- compatible), a barrel shifter, 24-bit addressing, an instruction cache, and a direct memory access (dma) controller (see figure 1 ). the dsp56321 offers 275 million multiply- accumulates per second (mmacs) performance, attaining 550 mmacs when the efcop is in use. it operates with an internal 275 mhz clock with a 1.6 volt core and independent 3.3 volt input/output (i/o) power. by operating in parallel with the core, the efcop provides overall enhanced performance and signal quality with no impact on channel throughput or total channel support. this device is pin-compatible with the freescale dsp56303, dsp56l307, dsp56309, and dsp56311. figure 1. dsp56321 block diagram ya b xab pa b ydb xdb pdb gdb modb/irqb modc/irqc 10 modd/irqd dsp56300 6 16 24-bit 24 18 ddb dab peripheral core ym_eb xm_eb pm_eb pio_eb expansion area 6 5 3 reset moda/irqa pinit/nmi extal xtal address control data address generation unit six channel dma unit program interrupt controller program decode controller program address generator data alu 24 24 + 56 56-bit mac two 56-bit accumulators 56-bit barrel shifter power management external bus interface and i - cache control memory expansion area de program ram 32 k 24 bits x data ram 80 k 24 bits y data ram 80 k 24 bits external address bus switch sci efcop essi hi08 tr i p l e timer or 31 k 24 bits instruction cache 1024 24 bits bootstrap rom and once? jtag pll clock generator internal data bus switch external data bus switch the dsp56321 is intended for applications requiring a large amount of internal memory, such as networking and wireless infrastructure applications. the onboard efcop can accelerate general filtering applications, such as echo-cancellation applications, correlation, and general-purpose convolution- based algorithms. what?s new? rev. 11 includes the following changes: adds lead-free packaging and part numbers.
dsp56321 technical data, rev. 11 ii freescale semiconductor table of contents data sheet conventions ......................................................................................................... ..............................ii features ....................................................................................................................... ........................................iii target applications ............................................................................................................ ................................. iv product documentation .......................................................................................................... .............................v chapter 1 signals/connections 1.1 power ....................................................................................................................... .........................................1-3 1.2 ground ...................................................................................................................... ........................................1-3 1.3 clock ....................................................................................................................... ..........................................1-3 1.4 external memory expansion port (port a) ..................................................................................... .................1-4 1.5 interrupt and mode control .................................................................................................. ............................1-6 1.6 host interface (hi08) ....................................................................................................... .................................1-7 1.7 enhanced synchronous serial interface 0 (essi0) ............................................................................. ...........1-10 1.8 enhanced synchronous serial interface 1 (essi1) ............................................................................. ...........1-11 1.9 serial communication interface (sci) ........................................................................................ ...................1-12 1.10 timers ..................................................................................................................... ........................................1-13 1.11 jtag and once interface .................................................................................................... ..........................1-14 chapter 2 specifications 2.1 maximum ratings............................................................................................................. ................................2-1 2.2 thermal characteristics ..................................................................................................... ...............................2-2 2.3 dc electrical characteristics............................................................................................... .............................2-2 2.4 ac electrical characteristics ............................................................................................... .............................2-3 chapter 3 packaging 3.1 package description ......................................................................................................... ................................3-2 3.2 map-bga package mechanical drawing .......................................................................................... ...........3-10 chapter 4 design considerations 4.1 thermal design considerations............................................................................................... .........................4-1 4.2 electrical design considerations............................................................................................ ..........................4-2 4.3 power consumption considerations............................................................................................ .....................4-3 4.4 input (extal) jitter requirements ........................................................................................... ......................4-4 appendix a power consumption benchmark data sheet conventions overbar indicates a signal that is active when pulled low (for example, the reset pin is active when low.) ?asserted? means that a high true (active high) signal is high or that a low true (active low) signal is low ?deasserted? means that a high true (active high) signal is low or that a low true (active low) signal is high examples: signal/symbol logic state signal state voltage pin true asserted v il /v ol pin false deasserted v ih /v oh pin true asserted v ih /v oh pin false deasserted v il /v ol note: values for v il , v ol , v ih , and v oh are defined by individual product specifications.
dsp56321 technical data, rev. 11 freescale semiconductor iii features ta bl e 1 lists the features of the dsp56321 device. table 1. dsp56321 features feature description high-performance dsp56300 core 275 million multiply-accumulates per second (mmacs) (550 mmacs using the efcop in filtering applications) with a 275 mhz clock at 1.6 v core and 3.3 v i/o object code compatible with the dsp56000 core with highly parallel instruction set data arithmetic logic unit (data alu) with fully pipelined 24 24-bit parallel multiplier-accumulator (mac), 56-bit parallel barrel shifter (fast shift and normalization; bit stream generation and parsing), conditional alu instructions, and 24-bit or 16-bit arithmetic support under software control program control unit (pcu) with position independent code (pic) support, addressing modes optimized for dsp applications (including immediate offsets), internal instruction cache controller, internal memory- expandable hardware stack, nested hardware do loops, and fast auto-return interrupts direct memory access (dma) with six dma channels supporting internal and external accesses; one-, two- , and three-dimensional transfers (including circular buffering); end-of-block-transfer interrupts; and triggering from interrupt lines and all peripherals phase-lock loop (pll) allows change of low-power divide factor (df) without loss of lock and output clock with skew elimination hardware debugging support including on-chip emulation (once) module, joint test action group (jtag) test access port (tap) enhanced filter coprocessor (efcop) internal 24 24-bit filtering and echo-cancellation coprocessor that runs in parallel to the dsp core operation at the same frequency as the core (up to 275 mhz) support for a variety of filter modes, some of which are optimized for cellular base station applications: real finite impulse response (fir) with real taps complex fir with complex taps complex fir generating pure real or pure imaginary outputs alternately a 4-bit decimation factor in fir filters, thus providing a decimation ratio up to 16 direct form 1 (dfi) infinite impulse response (iir) filter direct form 2 (dfii) iir filter four scaling factors (1, 4, 8, 16) for iir output adaptive fir filter with true least mean square (lms) coefficient updates adaptive fir filter with delayed lms coefficient updates internal peripherals enhanced 8-bit parallel host interface (hi08) supports a variety of buses (for example, isa) and provides glueless connection to a number of industry-standard microcomputers, microprocessors, and dsps two enhanced synchronous serial interfaces (essi), each with one receiver and three transmitters (allows six-channel home theater) serial communications interface (sci) with baud rate generator triple timer module up to 34 programmable general-purpose input/output (gpio) pins, depending on which peripherals are enabled
dsp56321 technical data, rev. 11 iv freescale semiconductor target applications dsp56321 applications require high performance, low power, small packaging, and a large amount of internal memory. the efcop can accelerate general filtering applications. examples include: wireless and wireline infrastructure applications multi-channel wireless local loop systems security encryption systems home entertainment systems dsp resource boards high-speed modem banks ip telephony internal memories 192 24-bit bootstrap rom 192 k 24-bit ram total program ram, instruction cache, x data ram, and y data ram sizes are programmable: external memory expansion data memory expansion to two 256 k 24-bit word memory spaces using the standard external address lines program memory expansion to one 256 k 24-bit words memory space using the standard external address lines external memory expansion port chip select logic for glueless interface to static random access memory (srams) power dissipation very low-power cmos design wait and stop low-power standby modes fully static design specified to operate down to 0 hz (dc) optimized power management circuitry (instruction-dependent, peripheral-dependent, and mode- dependent) packaging molded array plastic-ball grid array (map-bga) package in lead-free or lead-bearing versions. table 1 . dsp56321 features (continued) feature description : program ram size instruction cache size x data ram size* y data ram size* instruction cache msw2 msw1 msw0 32 k 24-bit 0 80 k 24-bit 80 k 24-bit disabled 0 0 0 31 k 24-bit 1024 24-bit 80 k 24-bit 80 k 24-bit enabled 0 0 0 40 k 24-bit 0 76 k 24-bit 76 k 24-bit disabled 0 0 1 39 k 24-bit 1024 24-bit 76 k 24-bit 76 k 24-bit enabled 0 0 1 48 k 24-bit 0 72 k 24-bit 72 k 24-bit disabled 0 1 0 47 k 24-bit 1024 24-bit 72 k 24-bit 72 k 24-bit enabled 0 1 0 64 k 24-bit 0 64 k 24-bit 64 k 24-bit disabled 0 1 1 63 k 24-bit 1024 24-bit 64 k 24-bit 64 k 24-bit enabled 0 1 1 72 k 24-bit 0 60 k 24-bit 60 k 24-bit disabled 1 0 0 71 k 24-bit 1024 24-bit 60 k 24-bit 60 k 24-bit enabled 1 0 0 80 k 24-bit 0 56 k 24-bit 56 k 24-bit disabled 1 0 1 79 k 24-bit 1024 24-bit 56 k 24-bit 56 k 24-bit enabled 1 0 1 96 k 24-bit 0 48 k 24-bit 48 k 24-bit disabled 1 1 0 95 k 24-bit 1024 24-bit 48 k 24-bit 48 k 24-bit enabled 1 1 0 112 k 24-bit 0 40 k 24-bit 40 k 24-bit disabled 1 1 1 111 k 24-bit 1024 24-bit 40 k 24-bit 40 k 24-bit enabled 1 1 1 *includes 12 k 24-bit shared memory (that is, 24 k total memory shared by the core and the efcop)
dsp56321 technical data, rev. 11 freescale semiconductor v product documentation the documents listed in table 2 are required for a complete description of the dsp56321 device and are necessary to design properly with the part. documentation is available from a local freescale distributor, a freescale semiconductor sales office, or a freescale semiconductor literature distribution center. for documentation updates, visit the freescale dsp website. see the contact information on the back cover of this document. table 2. dsp56321 documentation name description order number dsp56321 reference manual detailed functional description of the dsp56321 memory configuration, operation, and register programming dsp56321rm dsp56300 family manual detailed description of the dsp56300 family processor core and instruction set dsp56300fm application notes documents describing specific applications or optimized device operation including code examples see the dsp56321 product website
dsp56321 technical data, rev. 11 vi freescale semiconductor
dsp56321 technical data, rev. 11 freescale semiconductor 1-1 signals/connections 1 the dsp56321 input and output signals are organized into functional groups as shown in ta b le 1 -1 . figure 1-1 diagrams the dsp56321 signals by functional group. the remainder of this chapter describes the signal pins in each functional group. note: this chapter refers to a number of configuration registers used to select individual multiplexed signal functionality. see the dsp56321 reference manual for details on these configuration registers. table 1-1. dsp56321 functional signal groupings functional group number of signals power (v cc ) 20 ground (gnd) 66 clock 2 address bus port a 1 18 data bus 24 bus control 10 interrupt and mode control 6 host interface (hi08) port b 2 16 enhanced synchronous serial interface (essi) ports c and d 3 12 serial communication interface (sci) port e 4 3 timer 3 once/jtag port 6 notes: 1. port a signals define the external memory interface port, including the external address bus, data bus, and control signals. 2. port b signals are the hi08 port signals multiplexed with the gpio signals. 3. port c and d signals are the two essi port signals multiplexed with the gpio signals. 4. port e signals are the sci port signals multiplexed with the gpio signals. 5. eight signal lines are not connected internally. these are designated as no connect (nc) in the package description (see chapter 3 ). there are also two reserved lines.
dsp56321 technical data, rev. 11 1-2 freescale semiconductor signals/connections figure 1-1. signals identified by functional group notes: 1. the hi08 port supports a non-multiplexed or a multiplexed bus, single or double data strobe (ds), and single or double host request (hr) configurations. since each of these modes is configured independently, any combination of these modes is possible. these hi08 signals can also be configured alternatively as gpio signals (pb[0?15]). signals with dual designations (for example, has /has) have configurable polarity. 2. the essi0, essi1, and sci signals are multiplexed with the port c gpio signals (pc[0?5]), port d gpio signals (pd[0?5]), and port e gpio signals (pe[0?2]), respectively. 3. tio[0?2] can be configured as gpio signals. dsp56321 24 18 external address bus external data bus external bus control enhanced synchronous serial interface port 0 (essi0) 2 timers 3 once/ jtag port power inputs: core logic i/o address bus data bus bus control hi08 essi/sci/timer a[0?17] d[0?23] aa[0?3] rd wr ta br bg bb tck tdi tdo tms trst de v ccql v ccqh v cca v ccd v ccc v cch v ccs 5 serial communications interface (sci) port 2 4 2 2 grounds: ground plane gnd 66 interrupt/ mode control moda modb modc modd reset pinit host interface (hi08) port 1 non-multiplexed bus h[0?7] ha0 ha1 ha2 hcs/ hcs single ds hrw hds /hds single hr hreq /hreq hack /hack rxd txd sclk sc0[0?2] sck0 srd0 std0 tio0 tio1 tio2 8 3 3 extal xtal clock enhanced synchronous serial interface port 1 (essi1) 2 sc1[0?2] sck1 srd1 std1 3 multiplexed bus had[0?7] has /has ha8 ha9 ha10 double ds hrd /hrd hwr /hwr double hr htrq /htrq hrrq /hrrq port b gpio pb[0?7] pb8 pb9 pb10 pb13 pb11 pb12 pb14 pb15 port e gpio pe0 pe1 pe2 port c gpio pc[0?2] pc3 pc4 pc5 port d gpio pd[0?2] pd3 pd4 pd5 timer gpio tio0 tio1 tio2 port a 4 irqa irqb irqc irqd 3 reset during reset after reset nmi
power dsp56321 technical data, rev. 11 freescale semiconductor 1-3 1.1 power 1.2 ground 1.3 clock table 1-2. power inputs power name description v ccql quiet core (low) power ?an isolated power for the core processing and clock logic. this input must be isolated externally from all other chip power inputs. v ccqh quiet external (high) power ?a quiet power source for i/o lines. this input must be tied externally to all other chip power inputs , except v ccql . v cca address bus power ?an isolated power for sections of the address bus i/o drivers. this input must be tied externally to all other chip power inputs, except v ccql . v ccd data bus power ?an isolated power for sections of the data bus i/o drivers. this input must be tied externally to all other chip power inputs, except v ccql . v ccc bus control power ?an isolated power for the bus control i/o drivers. this input must be tied externally to all other chip power inputs , except v ccql . v cch host power ?an isolated power for the hi08 i/o drivers. this input must be tied externally to all other chip power inputs , except v ccql . v ccs essi, sci, and timer power ?an isolated power for the essi, sci, and timer i/o drivers. this input must be tied externally to all other chip power inputs, except v ccql . note: the user must provide adequate external decoupling capacitors for all power connections. table 1-3. grounds name description gnd ground ?connected to an internal device ground plane. note: the user must provide adequate external decoupling capacitors for all gnd connections. table 1-4. clock signals signal name type state during reset signal description extal input input external clock/crystal input ?interfaces the internal crystal oscillator input to an external crystal or an external clock. xtal output chip-driven crystal output ?connects the internal crystal oscillator output to an external crystal. if an external clock is used, leave xtal unconnected.
dsp56321 technical data, rev. 11 1-4 freescale semiconductor signals/connections 1.4 external memory expansion port (port a) note: when the dsp56321 enters a low-power standby mode (stop or wait), it releases bus mastership and tri- states the relevant port a signals: a[0?17] , d[0?23] , aa[0 ? 3] , rd , wr , bb . 1.4.1 external address bus 1.4.2 external data bus 1.4.3 external bus control table 1-5. external address bus signals signal name type state during reset, stop, or wait signal description a[0?17] output tri-stated address bus ?when the dsp is the bus master, a[0?17] are active-high outputs that specify the address for external program and data memory accesses. otherwise, the signals are tri-stated. to minimize power dissipation, a[0?17] do not change state when external memory spaces are not being accessed. table 1-6. external data bus signals signal name type state during reset state during stop or wait signal description d[0?23] input/ output ignored input last state: input : ignored output : last value data bus ?when the dsp is the bus master, d[0?23] are active-high, bidirectional input/outputs that provide the bidirectional data bus for external program and data memory accesses. otherwise, d[0?23] drivers are tri- stated. if the last state is output, these lines have weak keepers to maintain the last output state if all drivers are tri- stated. table 1-7. external bus control signals signal name type state during reset, stop, or wait signal description aa[0?3] output tri-stated address attribute ?when defined as aa, these signals can be used as chip selects or additional address lines. the default use defines a priority scheme under which only one aa signal can be asserted at a time. setting the aa priority disable (apd) bit (bit 14) of the operating mode register, the priority mechanism is disabled and the lines can be used together as four external lines that can be decoded externally into 16 chip select signals. rd output tri-stated read enable ?when the dsp is the bus master, rd is an active-low output that is asserted to read external memory on the data bus (d[0?23]). otherwise, rd is tri-stated. wr output tri-stated write enable ?when the dsp is the bus master, wr is an active-low output that is asserted to write external memory on the data bus (d[0?23]). otherwise, the signals are tri-stated.
external memory expansion port (port a) dsp56321 technical data, rev. 11 freescale semiconductor 1-5 ta input ignored input transfer acknowledge ?if the dsp56321 is the bus master and there is no external bus activity, or the dsp56321 is not the bus master, the ta input is ignored. the ta input is a data transfer acknowledge (dtack) function that can extend an external bus cycle indefinitely. any number of wait states (1, 2. . .infinity) can be added to the wait states inserted by the bus control register (bcr) by keeping ta deasserted. in typical operation, ta is deasserted at the start of a bus cycle, is asserted to enable completion of the bus cycle, and is deasserted before the next bus cycle. the current bus cycle completes one clock period after ta is asserted synchronous to clkout. the number of wait states is determined by the ta input or by the bcr, whichever is longer. the bcr can be used to set the minimum number of wait states in external bus cycles. to use the ta functionality, the bcr must be programmed to at least one wait state. a zero wait state access cannot be extended by ta deassertion; otherwise, improper operation may result. br output reset: output (deasserted) state during stop/wait depends on brh bit setting: brh = 0: output (deasserted) brh = 1: maintains last state (that is, if asserted, remains asserted) bus request ?asserted when the dsp requests bus mastership. br is deasserted when the dsp no longer needs the bus. br may be asserted or deasserted independently of whether the dsp56321 is a bus master or a bus slave. bus ?parking? allows br to be deasserted even though the dsp56321 is the bus master. (see the description of bus ?parking? in the bb signal description.) the bus request hold (brh) bit in the bcr allows br to be asserted under software control even though the dsp does not need the bus. br is typically sent to an external bus arbitrator that controls the priority, parking, and tenure of each master on the same external bus. br is affected only by dsp requests for the external bus, never for the internal bus. during hardware reset, br is deasserted and the arbitration is reset to the bus slave state. bg input ignored input bus grant ?asserted by an external bus arbitration circuit when the dsp56321 becomes the next bus master. when bg is asserted, the dsp56321 must wait until bb is deasserted before taking bus mastership. when bg is deasserted, bus mastership is typically given up at the end of the current bus cycle. this may occur in the middle of an instruction that requires more than one external bus cycle for execution. to ensure proper operation, the user must set the asynchronous bus arbitration enable (abe) bit (bit 13) in the operating mode register. when this bit is set, bg and bb are synchronized internally. this adds a required delay between the deassertion of an initial bg input and the assertion of a subsequent bg input. bb input/ output ignored input bus busy ?indicates that the bus is active. only after bb is deasserted can the pending bus master become the bus master (and then assert the signal again). the bus master may keep bb asserted after ceasing bus activity regardless of whether br is asserted or deasserted. called ?bus parking,? this allows the current bus master to reuse the bus without rearbitration until another device requires the bus. bb is deasserted by an ?active pull-up? method (that is, bb is driven high and then released and held high by an external pull-up resistor). notes: 1. see bg for additional information. 2. bb requires an external pull-up resistor. table 1-7. external bus control signals (continued) signal name type state during reset, stop, or wait signal description
dsp56321 technical data, rev. 11 1-6 freescale semiconductor signals/connections 1.5 interrupt and mode control the interrupt and mode control signals select the chip operating mode as it comes out of hardware reset. after reset is deasserted, these inputs are hardware interrupt request lines. table 1-8. interrupt and mode control signal name type state during reset signal description moda irqa input input schmitt-trigger input mode select a ?moda, modb, modc, and modd select one of 16 initial chip operating modes, latched into the operating mode register when the reset signal is deasserted. external interrupt request a ?after reset, this input becomes a level- sensitive or negative-edge-triggered, maskable interrupt request input during normal instruction processing. if the processor is in the stop or wait standby state and irqa is asserted, the processor exits the stop or wait state. modb irqb input input schmitt-trigger input mode select b ?moda, modb, modc, and modd select one of 16 initial chip operating modes, latched into the operating mode register when the reset signal is deasserted. external interrupt request b ?after reset, this input becomes a level- sensitive or negative-edge-triggered, maskable interrupt request input during normal instruction processing. if the processor is in the wait standby state and irqb is asserted, the processor exits the wait state. modc irqc input input schmitt-trigger input mode select c ?moda, modb, modc, and modd select one of 16 initial chip operating modes, latched into the operating mode register when the reset signal is deasserted. external interrupt request c ?after reset, this input becomes a level- sensitive or negative-edge-triggered, maskable interrupt request input during normal instruction processing. if the processor is in the wait standby state and irqc is asserted, the processor exits the wait state. modd irqd input input schmitt-trigger input mode select d ?moda, modb, modc, and modd select one of 16 initial chip operating modes, latched into the operating mode register when the reset signal is deasserted. external interrupt request d ?after reset, this input becomes a level- sensitive or negative-edge-triggered, maskable interrupt request input during normal instruction processing. if the processor is in the wait standby state and irqd is asserted, the processor exits the wait state. reset input schmitt-trigger input reset ?places the chip in the reset state and resets the internal phase generator. the schmitt-trigger input allows a slowly rising input (such as a capacitor charging) to reset the chip reliably. when the reset signal is deasserted, the initial chip operating mode is latched from the moda, modb, modc, and modd inputs. the reset signal must be asserted after powerup. pinit nmi input input schmitt-trigger input pll initial ?during assertion of reset , the value of pinit determines whether the dpll is enabled or disabled. nonmaskable interrupt ?after reset deassertion and during normal instruction processing, this schmitt-trigger input is the negative-edge-triggered nmi request.
host interface (hi08) dsp56321 technical data, rev. 11 freescale semiconductor 1-7 1.6 host interface (hi08) the hi08 provides a fast, 8-bit, parallel data port that connects directly to the host bus. the hi08 supports a variety of standard buses and connects directly to a number of industry-standard microcomputers, microprocessors, dsps, and dma hardware. 1.6.1 host port usage considerations careful synchronization is required when the system reads multiple-bit registers that are written by another asynchronous system. this is a common problem when two asynchronous systems are connected (as they are in the host port). the considerations for proper operation are discussed in ta bl e 1 -9 . 1.6.2 host port configuration hi08 signal functions vary according to the programmed configuration of the interface as determined by the 16 bits in the hi08 port control register. table 1-9. host port usage considerations action description asynchronous read of receive byte registers when reading the receive byte registers, receive register high (rxh), receive register middle (rxm), or receive register low (rxl), the host interface programmer should use interrupts or poll the receive register data full (rxdf) flag that indicates data is available. this assures that the data in the receive byte registers is valid. asynchronous write to transmit byte registers the host interface programmer should not write to the transmit byte registers, transmit register high (txh), transmit register middle (txm), or transmit register low (txl), unless the transmit register data empty (txde) bit is set indicating that the transmit byte registers are empty. this guarantees that the transmit byte registers transfer valid data to the host receive (hrx) register. asynchronous write to host vector the host interface programmer must change the host vector (hv) register only when the host command bit (hc) is clear. this practice guarantees that the dsp interrupt control logic receives a stable vector. table 1-10. host interface signal name type state during reset 1,2 signal description h[0?7] had[0?7] pb[0?7] input/output input/output input or output ignored input host data? when the hi08 is programmed to interface with a non-multiplexed host bus and the hi function is selected, these signals are lines 0?7 of the bidirectional data bus. host address? when the hi08 is programmed to interface with a multiplexed host bus and the hi function is selected, these signals are lines 0?7 of the bidirectional multiplexed address/data bus. port b 0?7? when the hi08 is configured as gpio through the hi08 port control register, these signals are individually programmed as inputs or outputs through the hi08 data direction register.
dsp56321 technical data, rev. 11 1-8 freescale semiconductor signals/connections ha0 has /has pb8 input input input or output ignored input host address input 0 ?when the hi08 is programmed to interface with a nonmultiplexed host bus and the hi function is selected, this signal is line 0 of the host address input bus. host address strobe? when the hi08 is programmed to interface with a multiplexed host bus and the hi function is selected, this signal is the host address strobe (has) schmitt-trigger input. the polarity of the address strobe is programmable but is configured active-low (has ) following reset. port b 8 ?when the hi08 is configured as gpio through the hi08 port control register, this signal is individually programmed as an input or output through the hi08 data direction register. ha1 ha8 pb9 input input input or output ignored input host address input 1 ?when the hi08 is programmed to interface with a nonmultiplexed host bus and the hi function is selected, this signal is line 1 of the host address (ha1) input bus. host address 8 ?when the hi08 is programmed to interface with a multiplexed host bus and the hi function is selected, this signal is line 8 of the host address (ha8) input bus. port b 9 ?when the hi08 is configured as gpio through the hi08 port control register, this signal is individually programmed as an input or output through the hi08 data direction register. ha2 ha9 pb10 input input input or output ignored input host address input 2 ?when the hi08 is programmed to interface with a nonmultiplexed host bus and the hi function is selected, this signal is line 2 of the host address (ha2) input bus. host address 9 ?when the hi08 is programmed to interface with a multiplexed host bus and the hi function is selected, this signal is line 9 of the host address (ha9) input bus. port b 10 ?when the hi08 is configured as gpio through the hi08 port control register, this signal is individually programmed as an input or output through the hi08 data direction register. hcs /hcs ha10 pb13 input input input or output ignored input host chip select ?when the hi08 is programmed to interface with a nonmultiplexed host bus and the hi function is selected, this signal is the host chip select (hcs) input. the polarity of the chip select is programmable but is configured active-low (hcs ) after reset. host address 10 ?when the hi08 is programmed to interface with a multiplexed host bus and the hi function is selected, this signal is line 10 of the host address (ha10) input bus. port b 13 ?when the hi08 is configured as gpio through the hi08 port control register, this signal is individually programmed as an input or output through the hi08 data direction register. hrw hrd /hrd pb11 input input input or output ignored input host read/write ?when the hi08 is programmed to interface with a single- data-strobe host bus and the hi function is selected, this signal is the host read/write (hrw) input. host read data ?when the hi08 is programmed to interface with a double- data-strobe host bus and the hi function is selected, this signal is the hrd strobe schmitt-trigger input. the polarity of the data strobe is programmable but is configured as active-low (hrd ) after reset. port b 11 ?when the hi08 is configured as gpio through the hi08 port control register, this signal is individually programmed as an input or output through the hi08 data direction register. table 1-10. host interface (continued) signal name type state during reset 1,2 signal description
host interface (hi08) dsp56321 technical data, rev. 11 freescale semiconductor 1-9 hds /hds hwr /hwr pb12 input input input or output ignored input host data strobe ?when the hi08 is programmed to interface with a single- data-strobe host bus and the hi function is selected, this signal is the host data strobe (hds) schmitt-trigger input. the polarity of the data strobe is programmable but is configured as active-low (hds ) following reset. host write data ?when the hi08 is programmed to interface with a double- data-strobe host bus and the hi function is selected, this signal is the host write data strobe (hwr) schmitt-trigger input. the polarity of the data strobe is programmable but is configured as active-low (hwr ) following reset. port b 12 ?when the hi08 is configured as gpio through the hi08 port control register, this signal is individually programmed as an input or output through the hi08 data direction register. hreq /hreq htrq /htrq pb14 output output input or output ignored input host request ?when the hi08 is programmed to interface with a single host request host bus and the hi function is selected, this signal is the host request (hreq) output. the polarity of the host request is programmable but is configured as active-low (hreq ) following reset. the host request may be programmed as a driven or open-drain output. transmit host request ?when the hi08 is programmed to interface with a double host request host bus and the hi function is selected, this signal is the transmit host request (htrq) output. the polarity of the host request is programmable but is configured as active-low (htrq ) following reset. the host request may be programmed as a driven or open-drain output. port b 14 ?when the hi08 is configured as gpio through the hi08 port control register, this signal is individually programmed as an input or output through the hi08 data direction register. hack /hack hrrq /hrrq pb15 input output input or output ignored input host acknowledge ?when the hi08 is programmed to interface with a single host request host bus and the hi function is selected, this signal is the host acknowledge (hack) schmitt-trigger input. the polarity of the host acknowledge is programmable but is configured as active-low (hack ) after reset. receive host request ?when the hi08 is programmed to interface with a double host request host bus and the hi function is selected, this signal is the receive host request (hrrq) output. the polarity of the host request is programmable but is configured as active-low (hrrq ) after reset. the host request may be programmed as a driven or open-drain output. port b 15 ?when the hi08 is configured as gpio through the hi08 port control register, this signal is individually programmed as an input or output through the hi08 data direction register. notes: 1. in the stop state, the signal maintains the last state as follows: if the last state is input, the signal is an ignored input. if the last state is output, these lines have weak keepers that maintain the last output state even if the drivers are tri-s tated. 2. the wait processing state does not affect the signal state. table 1-10. host interface (continued) signal name type state during reset 1,2 signal description
dsp56321 technical data, rev. 11 1-10 freescale semiconductor signals/connections 1.7 enhanced synchronous serial interface 0 (essi0) two synchronous serial interfaces (essi0 and essi1) provide a full-duplex serial port for serial communication with a variety of serial devices, including one or more industry-standard codecs, other dsps, microprocessors, and peripherals that implement the freescale serial peripheral interface (spi). table 1-11. enhanced synchronous serial interface 0 signal name type state during reset 1,2 signal description sc00 pc0 input or output input or output ignored input serial control 0 ?for asynchronous mode, this signal is used for the receive clock i/o (schmitt-trigger input). for synchronous mode, this signal is used either for transmitter 1 output or for serial i/o flag 0. port c 0 ?the default configuration following reset is gpio input pc0. when configured as pc0, signal direction is controlled through the port c direction register. the signal can be configured as essi signal sc00 through the port c control register. sc01 pc1 input/output input or output ignored input serial control 1 ?for asynchronous mode, this signal is the receiver frame sync i/o. for synchronous mode, this signal is used either for transmitter 2 output or for serial i/o flag 1. port c 1 ?the default configuration following reset is gpio input pc1. when configured as pc1, signal direction is controlled through the port c direction register. the signal can be configured as an essi signal sc01 through the port c control register. sc02 pc2 input/output input or output ignored input serial control signal 2 ?the frame sync for both the transmitter and receiver in synchronous mode, and for the transmitter only in asynchronous mode. when configured as an output, this signal is the internally generated frame sync signal. when configured as an input, this signal receives an external frame sync signal for the transmitter (and the receiver in synchronous operation). port c 2 ?the default configuration following reset is gpio input pc2. when configured as pc2, signal direction is controlled through the port c direction register. the signal can be configured as an essi signal sc02 through the port c control register. sck0 pc3 input/output input or output ignored input serial clock ?provides the serial bit rate clock for the essi. the sck0 is a clock input or output, used by both the transmitter and receiver in synchronous modes or by the transmitter in asynchronous modes. although an external serial clock can be independent of and asynchronous to the dsp system clock, it must exceed the minimum clock cycle time of 6t (that is, the system clock frequency must be at least three times the external essi clock frequency). the essi needs at least three dsp phases inside each half of the serial clock. port c 3 ?the default configuration following reset is gpio input pc3. when configured as pc3, signal direction is controlled through the port c direction register. the signal can be configured as an essi signal sck0 through the port c control register. srd0 pc4 input input or output ignored input serial receive data ?receives serial data and transfers the data to the essi receive shift register. srd0 is an input when data is received. port c 4 ?the default configuration following reset is gpio input pc4. when configured as pc4, signal direction is controlled through the port c direction register. the signal can be configured as an essi signal srd0 through the port c control register.
enhanced synchronous serial interface 1 (essi1) dsp56321 technical data, rev. 11 freescale semiconductor 1-11 1.8 enhanced synchronous serial interface 1 (essi1) std0 pc5 output input or output ignored input serial transmit data ?transmits data from the serial transmit shift register. std0 is an output when data is transmitted. port c 5 ?the default configuration following reset is gpio input pc5. when configured as pc5, signal direction is controlled through the port c direction register. the signal can be configured as an essi signal std0 through the port c control register. notes: 1. in the stop state, the signal maintains the last state as follows: if the last state is input, the signal is an ignored input. if the last state is output, these lines have weak keepers that maintain the last output state even if the drivers are tri-s tated. 2. the wait processing state does not affect the signal state. table 1-12. enhanced serial synchronous interface 1 signal name type state during reset 1,2 signal description sc10 pd0 input or output input or output ignored input serial control 0 ?for asynchronous mode, this signal is used for the receive clock i/o (schmitt-trigger input). for synchronous mode, this signal is used either for transmitter 1 output or for serial i/o flag 0. port d 0 ?the default configuration following reset is gpio input pd0. when configured as pd0, signal direction is controlled through the port d direction register. the signal can be configured as an essi signal sc10 through the port d control register. sc11 pd1 input/output input or output ignored input serial control 1 ?for asynchronous mode, this signal is the receiver frame sync i/o. for synchronous mode, this signal is used either for transmitter 2 output or for serial i/o flag 1. port d 1 ?the default configuration following reset is gpio input pd1. when configured as pd1, signal direction is controlled through the port d direction register. the signal can be configured as an essi signal sc11 through the port d control register. sc12 pd2 input/output input or output ignored input serial control signal 2 ?the frame sync for both the transmitter and receiver in synchronous mode and for the transmitter only in asynchronous mode. when configured as an output, this signal is the internally generated frame sync signal. when configured as an input, this signal receives an external frame sync signal for the transmitter (and the receiver in synchronous operation). port d 2 ?the default configuration following reset is gpio input pd2. when configured as pd2, signal direction is controlled through the port d direction register. the signal can be configured as an essi signal sc12 through the port d control register. table 1-11. enhanced synchronous serial interface 0 (continued) signal name type state during reset 1,2 signal description
dsp56321 technical data, rev. 11 1-12 freescale semiconductor signals/connections 1.9 serial communication interface (sci) the sci provides a full duplex port for serial communication with other dsps, microprocessors, or peripherals such as modems. sck1 pd3 input/output input or output ignored input serial clock ?provides the serial bit rate clock for the essi. the sck1 is a clock input or output used by both the transmitter and receiver in synchronous modes or by the transmitter in asynchronous modes. although an external serial clock can be independent of and asynchronous to the dsp system clock, it must exceed the minimum clock cycle time of 6t (that is, the system clock frequency must be at least three times the external essi clock frequency). the essi needs at least three dsp phases inside each half of the serial clock. port d 3 ?the default configuration following reset is gpio input pd3. when configured as pd3, signal direction is controlled through the port d direction register. the signal can be configured as an essi signal sck1 through the port d control register. srd1 pd4 input input or output ignored input serial receive data ?receives serial data and transfers the data to the essi receive shift register. srd1 is an input when data is being received. port d 4 ?the default configuration following reset is gpio input pd4. when configured as pd4, signal direction is controlled through the port d direction register. the signal can be configured as an essi signal srd1 through the port d control register. std1 pd5 output input or output ignored input serial transmit data ?transmits data from the serial transmit shift register. std1 is an output when data is being transmitted. port d 5 ?the default configuration following reset is gpio input pd5. when configured as pd5, signal direction is controlled through the port d direction register. the signal can be configured as an essi signal std1 through the port d control register. notes: 1. in the stop state, the signal maintains the last state as follows: if the last state is input, the signal is an ignored input. if the last state is output, these lines have weak keepers that maintain the last output state even if the drivers are tri-s tated. 2. the wait processing state does not affect the signal state. table 1-13. serial communication interface signal name type state during reset 1,2 signal description rxd pe0 input input or output ignored input serial receive data ?receives byte-oriented serial data and transfers it to the sci receive shift register. port e 0 ?the default configuration following reset is gpio input pe0. when configured as pe0, signal direction is controlled through the port e direction register. the signal can be configured as an sci signal rxd through the port e control register. txd pe1 output input or output ignored input serial transmit data ?transmits data from the sci transmit data register. port e 1 ?the default configuration following reset is gpio input pe1. when configured as pe1, signal direction is controlled through the port e direction register. the signal can be configured as an sci signal txd through the port e control register. table 1-12. enhanced serial synchronous interface 1 (continued) signal name type state during reset 1,2 signal description
timers dsp56321 technical data, rev. 11 freescale semiconductor 1-13 1.10 timers the dsp56321 has three identical and independent timers. each timer can use internal or external clocking and can either interrupt the dsp56321 after a specified number of events (clocks) or signal an external device after counting a specific number of internal events. sclk pe2 input/output input or output ignored input serial clock ?provides the input or output clock used by the transmitter and/or the receiver. port e 2 ?the default configuration following reset is gpio input pe2. when configured as pe2, signal direction is controlled through the port e direction register. the signal can be configured as an sci signal sclk through the port e control register. notes: 1. in the stop state, the signal maintains the last state as follows: if the last state is input, the signal is an ignored input. if the last state is output, these lines have weak keepers that maintain the last output state even if the drivers are tri-s tated. 2. the wait processing state does not affect the signal state. table 1-14. triple timer signals signal name type state during reset 1,2 signal description tio0 input or output ignored input timer 0 schmitt-trigger input/output ? when timer 0 functions as an external event counter or in measurement mode, tio0 is used as input. when timer 0 functions in watchdog, timer, or pulse modulation mode, tio0 is used as output. the default mode after reset is gpio input. tio0 can be changed to output or configured as a timer i/o through the timer 0 control/status register (tcsr0). tio1 input or output ignored input timer 1 schmitt-trigger input/output ? when timer 1 functions as an external event counter or in measurement mode, tio1 is used as input. when timer 1 functions in watchdog, timer, or pulse modulation mode, tio1 is used as output. the default mode after reset is gpio input. tio1 can be changed to output or configured as a timer i/o through the timer 1 control/status register (tcsr1). tio2 input or output ignored input timer 2 schmitt-trigger input/output ? when timer 2 functions as an external event counter or in measurement mode, tio2 is used as input. when timer 2 functions in watchdog, timer, or pulse modulation mode, tio2 is used as output. the default mode after reset is gpio input. tio2 can be changed to output or configured as a timer i/o through the timer 2 control/status register (tcsr2). notes: 1. in the stop state, the signal maintains the last state as follows: if the last state is input, the signal is an ignored input. if the last state is output, these lines have weak keepers that maintain the last output state even if the drivers are tri-s tated. 2. the wait processing state does not affect the signal state. table 1-13. serial communication interface (continued) signal name type state during reset 1,2 signal description
dsp56321 technical data, rev. 11 1-14 freescale semiconductor signals/connections 1.11 jtag and once interface the dsp56300 family and in particular the dsp56321 support circuit-board test strategies based on the ieee ? std. 1149.1? test access port and boundary scan architecture, the industry standard developed under the sponsorship of the test technology committee of ieee and the jtag. the once module provides a means to interface nonintrusively with the dsp56300 core and its peripherals so that you can examine registers, memory, or on-chip peripherals. functions of the once module are provided through the jtag tap signals. for programming models, see the chapter on debugging support in the dsp56300 family manual . table 1-15. jtag/once interface signal name type state during reset signal description tck input input test clock ?a test clock input signal to synchronize the jtag test logic. tdi input input test data input ?a test data serial input signal for test instructions and data. tdi is sampled on the rising edge of tck and has an internal pull-up resistor. tdo output tri-stated test data output ?a test data serial output signal for test instructions and data. tdo is actively driven in the shift-ir and shift-dr controller states. tdo changes on the falling edge of tck. tms input input test mode select ?sequences the test controller?s state machine. tms is sampled on the rising edge of tck and has an internal pull-up resistor. trst input input test reset ?i nitializes the test controller asynchronously. trst has an internal pull-up resistor. trst must be asserted during and after power-up (see eb610/d for details). de input/ output input debug event ?as an input, initiates debug mode from an external command controller, and, as an open-drain output, acknowledges that the chip has entered debug mode. as an input, de causes the dsp56300 core to finish executing the current instruction, save the instruction pipeline information, enter debug mode, and wait for commands to be entered from the debug serial input line. this signal is asserted as an output for three clock cycles when the chip enters debug mode as a result of a debug request or as a result of meeting a breakpoint condition. the de has an internal pull-up resistor. this signal is not a standard part of the jtag tap controller. the signal connects directly to the once module to initiate debug mode directly or to provide a direct external indication that the chip has entered debug mode. all other interface with the once module must occur through the jtag port.
dsp56321 technical data, rev. 11 freescale semiconductor 2-1 specifications 2 the dsp56321 is fabricated in high-density cmos with transistor-transistor logic (ttl) compatible inputs and outputs. 2.1 maximum ratings in the calculation of timing requirements, adding a maximum value of one specification to a minimum value of another specification does not yield a reasonable sum. a maximum specification is calculated using a worst case variation of process parameter values in one direction. the minimum specification is calculated using the worst case for the same parameters in the opposite direction. therefore, a ?maximum? value for a specification never occurs in the same device that has a ?minimum? value for another specification; adding a maximum to a minimum represents a condition that can never exist. caution this device contains circuitry protecting against damage due to high static voltage or electrical fields; however, normal precautions should be taken to avoid exceeding maximum voltage ratings. reliability is enhanced if unused inputs are tied to an appropriate logic voltage level (for example, either gnd or v cc ). table 2-1. absolute maximum ratings rating 1 symbol value 1, 2 unit supply voltage 3 v ccql ?0.1 to 2.25 v input/output supply voltage 3 v ccqh ?0.3 to 4.35 v all input voltages v in gnd ? 0.3 to v ccqh + 0.3 v current drain per pin excluding v cc and gnd i 10 ma operating temperature range t j ?40 to +100 c storage temperature t stg ?55 to +150 c notes: 1. gnd = 0 v, v ccql = 1.6 v 0.1 v, v ccqh = 3.3 v 0.3 v, t j = ?40c to +100c, cl = 50 pf 2. absolute maximum ratings are stress ratings only, and functional operation at the maximum is not guaranteed. stress beyond the maximum rating may affect device reliability or cause permanent damage to the device. 3. power-up sequence: during power-up, and throughout the dsp56321 operation, v ccqh voltage must always be higher or equal to v ccql voltage.
dsp56321 technical data, rev. 11 2-2 freescale semiconductor specifications 2.2 thermal characteristics 2.3 dc electrical characteristics table 2-2. thermal characteristics thermal resistance characteristic symbol map-bga value unit junction-to-ambient, natural convection, single-layer board (1s) 1,2 r ja 44 c/w junction-to-ambient, natural convection, four-layer board (2s2p) 1,3 r jma 25 c/w junction-to-ambient, @200 ft/min air flow, single-layer board (1s) 1,3 r jma 35 c/w junction-to-ambient, @200 ft/min air flow, four-layer board (2s2p) 1,3 r jma 22 c/w junction-to-board 4 r jb 13 c/w junction-to-case thermal resistance 5 r jc 7 c/w notes: 1. junction temperature is a function of die size, on-chip power dissipation, package thermal resistance, mounting site (board) temperature, ambient temperature, air flow, power dissipation of other components on the board, and board thermal resistance. 2. per semi g38-87 and jedec jesd51-2 with the single-layer board horizontal. 3. per jedec jesd51-6 with the board horizontal. 4. thermal resistance between the die and the printed circuit board per jedec jesd51-8. board temperature is measured on the top surface of the board near the package. 5. thermal resistance between the die and the case top surface as measured by the cold plate method (mil spec-883 method 1012.1). table 2-3. dc electrical characteristics 7 characteristics symbol min typ max unit supply voltage 1 : core (v ccql ) i/o (v ccqh , v cca , v ccd , v ccc , v cch , and v ccs ) 1.5 3.0 1.6 3.3 1.7 3.6 v v input high voltage d[0?23], bg , bb , ta mod/irq 2 reset , pinit/nmi and all jtag/essi/sci/timer/hi08 pins extal 9 v ih v ihp v ihx 2.0 2.0 0.8 v ccqh ? ? ? v ccqh + 0.3 v ccqh + 0.3 v ccqh v v v input low voltage d[0?23], bg , bb , ta , mod/irq 2 , reset , pinit all jtag/essi/sci/timer/hi08 pins extal 9 v il v ilp v ilx ?0.3 ?0.3 ?0.3 ? ? ? 0.8 0.8 0.2 v ccqh v v v input leakage current i in ?10 ? 10 a high impedance (off-state) input current (@ 2.4 v / 0.4 v) i tsi ?10 ? 10 a output high voltage 8 ttl (i oh = ?0.4 ma) 6 cmos (i oh = ?10 a) 6 v oh 2.4 v ccqh ? 0.01 ? ? ? ? v v output low voltage 8 ttl (i ol = 3.0 ma) 6 cmos (i ol = 10 a) 6 v ol ? ? ? ? 0.4 0.01 v v
ac electrical characteristics dsp56321 technical data, rev. 11 freescale semiconductor 2-3 2.4 ac electrical characteristics the timing waveforms shown in the ac electrical characteristics section are tested with a v il maximum of 0.3 v and a v ih minimum of 2.4 v for all pins except extal, which is tested using the input levels shown in notes 7 and 9 of the previous table. ac timing specifications, which are referenced to a device input signal, are measured in production with respect to the 50 percent point of the respective input signal?s transition. dsp56321 output levels are measured with the production test machine v ol and v oh reference levels set at 0.4 v and 2.4 v, respectively. note: although the minimum value for the frequency of extal is 0 mhz, the device ac test conditions are 16 mhz and rated speed with the dpll enabled. 2.4.1 internal clocks internal supply current: in normal mode 3 ? at 200 mhz ? at 220 mhz ? at 240 mhz ? at 275 mhz in wait mode 4 in stop mode 5 i cci i ccw i ccs ? ? ? ? ? ? 190 200 210 235 25 15 ? ? ? ? ? ? ma ma ma ma ma ma input capacitance 6 c in ? ? 10 pf notes: 1. power-up sequence: during power-up, and throughout the dsp56321 operation, v ccqh voltage must always be higher or equal to v ccql voltage. 2. refers to moda/irqa , modb/irqb , modc/irqc , and modd/irqd pins. 3. section 4.3 provides a formula to compute the estimated current requirements in normal mode. to obtain these results, all inputs must be terminated (that is, not allowed to float). measurements are based on synthetic intensive dsp benchmarks (see appendix a ). the power consumption numbers in this specification are 90 percent of the measured results of this benchmark. this reflects typical dsp applications. 4. to obtain these results, all inputs must be terminated (that is, not allowed to float). 5. to obtain these results, all inputs not disconnected at stop mode must be terminated (that is, not allowed to float), and the dpll and on-chip crystal oscillator must be disabled. 6. periodically sampled and not 100 percent tested. 7. v ccqh = 3.3 v 0.3 v, v cqlc = 1.6 v 0.1 v; t j = ?40c to +100 c, c l = 50 pf 8. this characteristic does not apply to xtal. 9. driving extal to the low v ihx or the high v ilx value may cause additional power consumption (dc current). to minimize power consumption, the minimum v ihx should be no lower than 0.9 v ccqh and the maximum v ilx should be no higher than 0.1 v ccqh . table 2-4. internal clocks characteristics symbol expression min typ max internal operating frequency with dpll disabled with dpll enabled f ? ? ef/2 (ef mf)/(pdf df) ? ? internal clock cycle time with dpll disabled with dpll enabled t c ? ? 2 et c et c pdf df/mf ? ? internal clock high period with dpll disabled with dpll enabled t h ? 0.49 t c et c ? ? 0.51 t c table 2-3. dc electrical characteristics 7 characteristics symbol min typ max unit
dsp56321 technical data, rev. 11 2-4 freescale semiconductor specifications 2.4.2 external clock operation the dsp56321 system clock is derived from the on-chip oscillator or is externally supplied. to use the on-chip oscillator, connect a crystal and associated resistor/capacitor components to extal and xtal; an example is shown in figure 2-1 . internal clock low period with dpll disabled with dpll enabled t l ? 0.49 t c et c ? ? 0.51 t c note: ef = external frequency; mf = multiplication factor = mfi + mfn/mfd; pdf = predivision factor; df = division factor; t c = internal clock cycle; et c = external clock cycle; t h = internal clock high; t l = internal clock low figure 2-1. crystal oscillator circuits table 2-5. external clock operation no. characteristics symbol 200 mhz 220 mhz 240 mhz 275 mhz min max min max min max min max 1 frequency of extal (extal pin frequency) 1 with dpll disabled with dpll enabled 2 ef defr = pdf pdfr 0 mhz 16 mhz 200 mhz 200 mhz 0 mhz 16 mhz 220 mhz 220 mhz 0 mhz 16 mhz 240 mhz 240 mhz 0 mhz 16 mhz 275 mhz 275 mhz 2 extal input high 3 with dpll disabled (46.7%?53.3% duty cycle 4 ) with dpll enabled (42.5%?57.5% duty cycle 4 ) et h 2.34 ns 2.13 ns 35.9 ns 2.12 ns 1.93 ns 35.9 ns 1.95 ns 1.77 ns 35.9 ns 1.70 ns 1.55 ns 35.9 ns 3 extal input low 4 with dpll disabled (46.7%?53.3% duty cycle 4 ) with dpll enabled (42.5%?57.5% duty cycle 4 ) et l 2.34 ns 2.13 ns 35.9 ns 2.12ns 1.93 ns 35.9 ns 1.95 ns 1.77 ns 35.9 ns 1.70 ns 1.55 ns 35.9 ns table 2-4. internal clocks (continued) characteristics symbol expression min typ max s uggeste d c omponent v a l ues: f osc = 16?32 mhz r = 1 m ? 10% c = 10 pf 10% calculations are for a 16?32 mhz crystal with the following parameters: shunt capacitance (c 0 ) of 5.2?7.3 pf, series resistance of 5?15 ? , and drive level of 2 mw. xtal1 c c r fundamental frequency crystal oscillator xtal extal note: make sure that in the pctl register: xtld (bit 2) = 0
ac electrical characteristics dsp56321 technical data, rev. 11 freescale semiconductor 2-5 note: if an externally-supplied square wave voltage source is used, disable the internal oscillator circuit after boot-up by setting xtld (pctl register bit 2 = 1?see the dsp56321 reference manual ). the external square wave source connects to extal and xtal is not used. figure 2-2 shows the extal input signal. 2.4.3 clock generator (clkgen) and digital pll (dpll) characteristics 4 extal cycle time 3 with dpll disabled with dpll enabled et c 5.0 ns 5.0 ns 62.5 ns 4.55 ns 4.55 ns 62.5 ns 4.17 ns 4.17 ns 62.5 ns 3.64 ns 3.64 ns 62.5 ns 7 instruction cycle time = i cyc = et c with dpll disabled with dpll enabled i cyc 10 ns 5.0 ns 1.6 s 9.09 ns 4.55 ns 1.6 s 8.33 ns 4.17 ns 1.6 s 7.28 ns 3.64 ns 1.6 s notes: 1. the rise and fall time of this external clock should be 2 ns maximum. 2. refer to table 2-6 for a description of pdf and pdfr. 3. measured at 50 percent of the input transition. 4. the indicated duty cycle is for the specified maximum frequency for which a part is rated. the minimum clock high or low time required for correction operation, however, remains the same at lower operating frequencies; therefore, when a lower clock frequency is used, the signal symmetry may vary from the specified duty cycle as long as the minimum high time and low time requirements are met. figure 2-2. external input clock timing table 2-6. clkgen and dpll characteristics characteristics symbol 200 mhz 220 mhz 240 mhz 275 mhz unit min max min max min max min max predivision factor pdf 1 116116116116? predivider output clock frequency range pdfr 16 32 16 32 16 32 16 32 mhz total multiplication factor 2 mf515515515515? multiplication factor integer part mfi 1 515515515515? multiplication factor numerator 3 mfn0127012701270127? multiplication factor denominator mfd 1 128 1 128 1 128 1 128 ? double clock frequency range ddfr 160 400 160 440 160 480 160 550 mhz phase lock-in time 4 dplt 6.8 5 150 6 6.8 5 150 6 6.8 5 150 6 6.8 5 150 6 s table 2-5. external clock operation (continued) no. characteristics symbol 200 mhz 220 mhz 240 mhz 275 mhz min max min max min max min max extal v ilx v ihx midpoint note: the midpoint is 0.5 (v ihx + v ilx ). et h et l et c 3 4 2
dsp56321 technical data, rev. 11 2-6 freescale semiconductor specifications 2.4.4 reset, stop, mode select, and interrupt timing notes: 1. refer to the dsp56321 user?s manual for a detailed description of register reset values. 2. the total multiplication factor (mf) includes both integer and fractional parts (that is, mf = mfi + mfn/mfd). 3. the numerator (mfn) should be less than the denominator (mfd). 4. dpll lock procedure duration is specified for the case when an external clock source is supplied to the extal pin. 5. frequency-only lock mode or non-integer mf, after partial reset. 6. frequency and phase lock mode, integer mf, after full reset. table 2-7. reset, stop, mode select, and interrupt timing 5 no. characteristics expression 200 mhz 220 mhz 240 mhz 275 mhz unit min max min max min max min max 8 delay from reset assertion to all pins at reset value 3 ??26?26?26?26ns 9 required reset duration 4 power on, external clock generator, dpll disabled power on, external clock generator, dpll enabled power on, internal oscillator during stop, xtal disabled during stop, xtal enabled during normal operation 50 et c 1000 et c 75000 et c 75000 et c 2.5 t c 2.5 t c 250.0 5.0 0.375 0.375 12.5 17 ? ? ? ? ? ? 227.5 4.55 0.341 0.341 11.38 16 ? ? ? ? ? ? 208.5 4.17 0.313 0.313 10.43 15 ? ? ? ? ? ? 182.0 3.64 0.273 0.273 9.1 9.1 ? ? ? ? ? ? ns s ms ms ns ns 10 delay from asynchronous reset deassertion to first external address output (internal reset deassertion) minimum maximum 3.25 t c + 2.0 18.25 ? ? 180 16.77 ? ? 163 15.55 ? ? 150 13.82 ? ? 140 ns ns 13 mode select setup time 30.0 ? 30.0 ? 30.0 ? 30.0 ? ns 14 mode select hold time 0.0 ? 0.0 ? 0.0 ? 0.0 ? ns 15 minimum edge-triggered interrupt request assertion width 4.0 ? 4.0 ? 4.0 ? 4.0 ? ns 16 minimum edge-triggered interrupt request deassertion width 4.0 ? 4.0 ? 4.0 ? 4.0 ? ns 17 delay from irqa , irqb , irqc , irqd , nmi assertion to external memory access address out valid caused by first interrupt instruction fetch caused by first interrupt instruction execution 4.25 t c + 2.0 7.25 t c + 2.0 23.25 38.25 ? ? 21.24 34.99 ? ? 19.72 32.23 ? ? 17.45 28.36 ? ? ns ns 18 delay from irqa , irqb , irqc , irqd , nmi assertion to general-purpose transfer output valid caused by first interrupt instruction execution 8.9 t c 44.5 ? 40.45 ? 37.0 ? 32.37 ? ns 19 delay from address output valid caused by first interrupt instruction execute to interrupt request deassertion for level sensitive fast interrupts 1, 6, 7 (ws + 3.75) t c ? 10.94 ? note 7 ? note 7 ? note 7 ? note 7 ns table 2-6. clkgen and dpll characteristics (continued) characteristics symbol 200 mhz 220 mhz 240 mhz 275 mhz unit min max min max min max min max
ac electrical characteristics dsp56321 technical data, rev. 11 freescale semiconductor 2-7 20 delay from rd assertion to interrupt request deassertion for level sensitive fast interrupts 1, 6, 7 (ws + 3.25) t c ? 10.94 ? note 7 ? note 7 ? note 7 ? note 7 ns 21 delay from wr assertion to interrupt request deassertion for level sensitive fast interrupts 1, 6, 7 sram ws = 3 sram ws 4 (ws + 3) t c ? 10.94 (ws + 2.5) t c ? 10.94 ? ? note 7 note 7 ? ? note 7 note 7 ? ? note 7 note 7 ? ? note 7 note 7 ns ns 24 duration for irqa assertion to recover from stop state 8.0 ? 8.0 ? 8.0 ? 8.0 ? ns 25 delay from irqa assertion to fetch of first instruction (when exiting stop) 2, 3 dpll is not active during stop (pctl bit 1 = 0) and stop delay is enabled (operating mode register bit 6 = 0) dpll is not active during stop (pctl bit 1 = 0) and stop delay is not enabled (operating mode register bit 6 = 1) dpll is active during stop (pctl bit 1 = 1; implies no stop delay) dplt + (128k t c ) dplt + (23.75 0.5) t c (10.0 1.75) t c 662.2 s 6.9 41.25 209.9 ms 188.8 58.8 662.2 s 6.9 37.5 209.9 ms 188.8 53.3 662.2 s 6.9 34.4 209.9 ms 188.8 49.0 662.2 s 6.9 30.0 209.9 ms 188.8 43.0 ? s ns 26 duration of level sensitive irqa assertion to ensure interrupt service (when exiting stop) 2, 3 dpll is not active during stop (pctl bit 1 = 0) and stop delay is enabled (operating mode register bit 6 = 0) dpll is not active during stop (pctl bit 1 = 0) and stop delay is not enabled (operating mode register bit 6 = 1) dpll is active during stop ((pctl bit 1 = 0; implies no stop delay) dplt + (128 k t c ) dplt + (20.5 0.5) t c 5.5 t c 805.4 150.1 27.5 ? ? ? 805.4 150.1 25 ? ? ? 805.4 150.1 22.9 ? ? ? 805.4 150.1 20.0 ? ? ? s s ns 27 interrupt request rate hi08, essi, sci, timer dma irq , nmi (edge trigger) irq , nmi (level trigger) 12t c 8t c 8t c 12t c ? ? ? ? 60.0 40.0 40.0 60.0 ? ? ? ? 54.6 36.4 36.4 54.6 ? ? ? ? 50.0 33.4 33.4 50.0 ? ? ? ? 43.7 29.2 29.2 43.7 ns ns ns ns 28 dma request rate data read from hi08, essi, sci data write to hi08, essi, sci timer irq , nmi (edge trigger) 6t c 7t c 2t c 3t c ? ? ? ? 30.0 35.0 10.0 15.0 ? ? ? ? 27.3 31.9 9.1 13.7 ? ? ? ? 25.0 29.2 8.3 12.5 ? ? ? ? 21.84 25.48 7.28 10.92 ns ns ns ns 29 delay from irqa , irqb , irqc , irqd , nmi assertion to external memory (dma source) access address out valid 4.25 t c + 2.0 23.25 ? 21.34 ? 19.72 ? 17.45 ? ns table 2-7. reset, stop, mode select, and interrupt timing 5 (continued) no. characteristics expression 200 mhz 220 mhz 240 mhz 275 mhz unit min max min max min max min max
dsp56321 technical data, rev. 11 2-8 freescale semiconductor specifications notes: 1. when fast interrupts are used and irqa , irqb , irqc , and irqd are defined as level-sensitive, timings 19 through 21 apply to prevent multiple interrupt service. to avoid these timing restrictions, the deasserted edge-triggered mode is recommended when fast interrupts are used. long interrupts are recommended for level-sensitive mode. 2. this timing depends on several settings: for dpll disable, using internal oscillator (dpll control register (pctl) bit 2 = 0) and oscillator disabled during stop (pc tl bit 1 = 0), a stabilization delay is required to assure that the oscillator is stable before programs are executed. resetting t he stop delay (operating mode register bit 6 = 0) provides the proper delay. while operating mode register bit 6 = 1 can be set, it is not recommended, and these specifications do not guarantee timings for that case. for dpll disable, using internal oscillator (pctl bit 2 = 0) and oscillator enabled during stop (pctl bit 1 = 1), no stabiliza tion delay is required and recovery is minimal (operating mode register bit 6 setting is ignored). for dpll disable, using external clock (pctl bit 2 = 1), no stabilization delay is required and recovery time is defined by the pctl bit 1 and operating mode register bit 6 settings. for dpll enable, if pctl bit 1 is 0, the dpll is shut down during stop. recovering from stop requires the dpll to lock. the dpll lock procedure duration is defined in ta ble 2-6 and will be refined after silicon characterization. this procedure is followed by the stop delay counter. stop recovery ends when the stop delay counter completes its count. the dplt value for dpll disable is 0. 3. periodically sampled and not 100 percent tested. 4. for an external clock generator, reset duration is measured while reset is asserted, v cc is valid, and the extal input is active and valid. for an internal oscillator, reset duration is measured while reset is asserted and v cc is valid. the specified timing reflects the crystal oscillator stabilization time after power-up. this number is affected both by the specifications of the crystal and other components connected to the oscillator and reflects worst case conditions. when the v cc is valid, but the other ?required reset duration? conditions (as specified above) have not been yet met, the device circuitry is in an uninitialized state that can result in significant power consumption and heat-up. designs should mini mize this state to the shortest possible duration. 5. v ccqh = 3.3 v 0.3 v, v ccql = 1.6 v 0.1 v; t j = ?40c to +100c, c l = 50 pf. 6. ws = number of wait states (measured in clock cycles, number of t c ). 7. use the expression to compute a maximum value. figure 2-3. reset timing table 2-7. reset, stop, mode select, and interrupt timing 5 (continued) no. characteristics expression 200 mhz 220 mhz 240 mhz 275 mhz unit min max min max min max min max v ih reset reset value first fetch all pins a[0?17] 8 9 10
ac electrical characteristics dsp56321 technical data, rev. 11 freescale semiconductor 2-9 figure 2-4. external fast interrupt timing figure 2-5. external interrupt timing (negative edge-triggered) a[0?17] rd a) first interrupt instruction execution general purpose i/o irqa , irqb , irqc , irqd , nmi b) general-purpose i/o irqa , irqb , irqc , irqd , nmi wr 20 21 19 17 18 first interrupt instruction execution/fetch irqa , irqb , irqc , irqd , nmi irqa , irqb , irqc , irqd , nmi 15 16
dsp56321 technical data, rev. 11 2-10 freescale semiconductor specifications figure 2-6. operating mode select timing figure 2-7. recovery from stop state using irqa figure 2-8. recovery from stop state using irqa interrupt service figure 2-9. external memory access (dma source) timing v ih v ih v il v ih v il 13 14 irqa , irqb , irqc , irqd , nmi reset moda, modb, modc, modd, pinit first instruction fetch irqa a[0?17] 24 25 irqa a[0?17] first irqa interrupt instruction fetch 26 25 29 dma source address first interrupt instruction execution a[0?17] rd wr irqa , irqb , irqc , irqd , nmi
ac electrical characteristics dsp56321 technical data, rev. 11 freescale semiconductor 2-11 2.4.5 external memory expansion port (port a) 2.4.5.1 sram timing table 2-8. sram timing no. characteristics symbol expression 1 200 mhz 220 mhz 240 mhz 275 mhz unit min max min max min max min max 100 address valid and aa assertion pulse width 2 t rc , t wc (ws + 2) t c ? 4.0 [3 ws 7] (ws + 3) t c ? 4.0 [ws 8] 21.0 51.0 ? 18.8 46.0 ? 16.9 41.9 ? 15.0 36.0 ? ns ns 101 address and aa valid to wr assertion t as 0.75 t c ? 3.0 [ws = 3] 1.25 t c ? 3.0 [ws 4] 0.75 3.25 ? ? 0.41 2.69 ? ? 0.13 2.21 ? ? ?0.27 1.54 ? ? ns ns 102 wr assertion pulse width t wp ws t c ? 4.0 [ws = 3] (ws ? 0.5) t c ? 4.0 [ws 4] 11.0 13.5 ? ? 9.65 11.93 ? ? 8.51 10.6 ? ? 6.9 8.72 ? ? ns ns 103 wr deassertion to address not valid t wr 1.25 t c ? 4.0 [3 ws 7] 2.25 t c ? 4.0 [ws 8] 2.25 7.25 ? ? 1.69 6.24 ? ? 1.21 5.38 ? ? 0.54 4.18 ? ? ns ns 104 address and aa valid to input data valid t aa , t ac (ws + 0.75) t c ? 5.8 [ws 3] ? 12.9 ? 11.2 ? 9.8 ? 7.84 ns 105 rd assertion to input data valid t oe (ws + 0.25) t c ? 6.5 [ws 3] ? 9.75 ? 8.29 ? 7.05 ? 5.31 ns 106 rd deassertion to data not valid (data hold time) t ohz 0.0 ? 0.0 ? 0.0 ? 0.0 ? ns 107 address valid to wr deassertion 2 t aw (ws + 0.75) t c ? 4.0 [ws 3] 14.75 ? 13.06 ? 11.64 ? 9.63 ? ns 108 data valid to wr deassertion (data setup time) t ds (t dw )(ws ? 0.25) t c ? 5.4 [ws 3] 8.35 ? 7.11 ? 6.07 ? 4.6 ? ns 109 data hold time from wr deassertion t dh 1.25 t c ? 4.0 [3 ws 7] 2.25 t c ? 4.0 [ws 8] 2.25 7.25 ? ? 1.69 6.23 ? ? 1.21 5.38 ? ? 0.54 4.18 ? ? ns ns 110 wr assertion to data active ?0.25 t c ? 4.0 [ws = 3] ?0.25 t c ? 4.0 [ws 4] ?2.75 ?5.25 ? ? ?2.86 ?5.14 ? ? ?2.96 ?5.04 ? ? ?3.1 ?4.91 ? ? ns ns 111 wr deassertion to data high impedance ?1.25 t c 6.25 ? 5.69 ? 5.21 ? 4.55 ? ns 112 previous rd deassertion to data active (write) ?2.25 t c ? 4.0 7.25 ? 6.23 ? 5.38 ? 4.18 ? ns 113 rd deassertion time ? 1.75 t c ? 3.0 [3 ws 7] 2.75 t c ? 3.0 [ws 8] 5.75 10.75 ? ? 4.96 9.51 ? ? 4.3 8.47 ? ? 3.36 7.0 ? ? ns ns 114 wr deassertion time 4 ?2.0 t c ? 3.0 [3 ws 7] 3.0 t c ? 3.0 [ws 8] 7.0 12.0 ? ? 6.1 10.6 ? ? 5.3 9.5 ? ? 4.27 7.91 ? ? ns ns
dsp56321 technical data, rev. 11 2-12 freescale semiconductor specifications 115 address valid to rd assertion ?0.5 t c ? 2.0 0.5 ? 0.3 ? 0.1 ? ?0.18 ? ns 116 rd assertion pulse width ? (ws + 0.25) t c ? 3.0 [ws 3] 13.25 ? 11.59 ? 10.55 ? 8.81 ? ns 117 rd deassertion to address not valid ?1.25 t c ? 4.0 [3 ws 7] 2.25 t c ? 4.0 [ws 8] 2.25 7.25 ? ? 1.69 6.24 ? ? 1.21 5.38 ? ? 0.54 4.18 ? ? ns ns 118 ta setup before rd or wr deassertion 5 ?0.25 t c + 2.0 3.25 ? 3.14 ? 3.04 ? 2.91 ? ns 119 ta hold after rd or wr deassertion ? 0?0?0?0?ns notes: 1. ws is the number of wait states specified in the bcr. the value is given for the minimum for a given category. (for example, for a category of [3 ws 7] timing is specified for 3 wait states.) three wait states is the minimum value otherwise. 2. timings 100 and 107 are guaranteed by design, not tested. 3. all timings are measured from 0.5 v ccqh to 0.5 v ccqh . 4. the ws number applies to the access in which the deassertion of wr occurs and assumes the next access uses a minimal number of wait states. 5. timing 118 is relative to the deassertion edge of rd or wr even if ta remains asserted. figure 2-10. sram read access table 2-8. sram timing (continued) no. characteristics symbol expression 1 200 mhz 220 mhz 240 mhz 275 mhz unit min max min max min max min max a[0?17] rd wr d[0?23] aa[0?3] 105 106 113 104 116 117 100 ta 118 data in 119 note: address lines a[0?17] hold their state after a read or write operation. aa[0?3] do not hold their state after a read or write operation.
ac electrical characteristics dsp56321 technical data, rev. 11 freescale semiconductor 2-13 2.4.5.2 asynchronous bus arbitration timings figure 2-11. sram write access table 2-9. asynchronous bus timings no. characteristics expression 200 mhz 220 mhz 240 mhz 275 mhz uni t min max min max min max min max 250 bb assertion window from bg input deassertion. 2.5 tc + 5 ? 17.5 ? 16.4 ? 15.4 ? 14.1 ns 251 delay from bb assertion to bg assertion 2 tc + 5 15 ? 14.1 ? 13.3 ? 12.27 ? ns notes: 1. bit 13 in the operating mode register must be set to enable asynchronous arbitration mode. 2. to guarantee timings 250 and 251, it is recommended that you assert non-overlapping bg inputs to different dsp56300 devices (on the same bus), as shown in figure 2-12 , where bg1 is the bg signal for one dsp56300 device while bg2 is the bg signal for a second dsp56300 device. a[0?17] wr rd data out d[0?23] aa[0?3] 100 102 101 107 114 108 109 103 ta 118 119 note: address lines a[0?17] hold their state after a read or write operation. aa[0?3] do not hold their state after a read or write operation.
dsp56321 technical data, rev. 11 2-14 freescale semiconductor specifications the asynchronous bus arbitration is enabled by internal synchronization circuits on bg and bb inputs. these synchronization circuits add delay from the external signal until it is exposed to internal logic. as a result of this delay, a dsp56300 part may assume mastership and assert bb , for some time after bg is deasserted. this is the reason for timing 250. once bb is asserted, there is a synchronization delay from bb assertion to the time this assertion is exposed to other dsp56300 components that are potential masters on the same bus. if bg input is asserted before that time, and bg is asserted and bb is deasserted, another dsp56300 component may assume mastership at the same time. therefore, some non-overlap period between one bg input active to another bg input active is required. timing 251 ensures that overlaps are avoided. 2.4.6 host interface timing figure 2-12. asynchronous bus arbitration timing table 2-10. host interface timings 1,2,12 no. characteristic 10 expression 200 mhz 220 mhz 240 mhz 275 mhz uni t min max min max min max min max 317 read data strobe assertion width 5 hack assertion width t c + 4.95 9.95 ? 9.05 ? 8.3 ? 7.77 ? ns 318 read data strobe deassertion width 5 hack deassertion width 4.95 ? 4.5 ? 4.13 ? 4.0 ? ns 319 read data strobe deassertion width 5 after ?last data register? reads 8,11 , or between two consecutive cvr, icr, or isr reads 3 hack deassertion width after ?last data register? reads 8,11 2.5 t c + 3.3 15.8 ? 14.7 ? 13.7 ? 12.39 ? ns 320 write data strobe assertion width 6 6.6 ? 6.0 ? 5.5 ? 5.1 ? ns 321 write data strobe deassertion width 8 hack write deassertion width after icr, cvr and ?last data register? writes after ivr writes, or after txh:txm:txl writes (with hlend= 0), or after txl:txm:txh writes (with hlend = 1) 2.5 t c + 3.3 15.8 8.25 ? ? 14.7 7.5 ? ? 13.7 6.88 ? ? 12.39 6.28 ? ? ns ns 322 has assertion width 4.95 ? 4.5 ? 4.13 ? 4.0 ? ns bg1 bb 251 bg2 250 250+251
ac electrical characteristics dsp56321 technical data, rev. 11 freescale semiconductor 2-15 323 has deassertion to data strobe assertion 4 0.0 ? 0.0 ? 0.0 ? 0.0 ? ns 324 host data input setup time before write data strobe deassertion 6 4.95 ? 4.5 ? 4.13 ? 4.0 ? ns 325 host data input hold time after write data strobe deassertion 6 1.65 ? 1.5 ? 1.38 ? 1.23 ? ns 326 read data strobe assertion to output data active from high impedance 5 hack assertion to output data active from high impedance 1.65 ? 1.5 ? 1.38 ? 1.23 ? ns 327 read data strobe assertion to output data valid 5 hack assertion to output data valid ? 14.78 ? 13.45 ? 12.32 ? 10.2 ns 328 read data strobe deassertion to output data high impedance 5 hack deassertion to output data high impedance ? 4.95 ? 4.5 ? 4.13 4.0 ? ns 329 output data hold time after read data strobe deassertion 5 output data hold time after hack deassertion 1.65 ? 1.5 ? 1.38 ? 1.23 ? ns 330 hcs assertion to read data strobe deassertion 5 t c + 4.95 9.95 ? 9.05 ? 8.3 ? 7.77 ? ns 331 hcs assertion to write data strobe deassertion 6 8?8?8?8?ns 332 hcs assertion to output data valid ? 17 ? 16 ? 15 ? 14 ns 333 hcs hold time after data strobe deassertion 4 0.0 ? 0.0 ? 0.0 ? 0.0 ? ns 334 address (had[0?7]) setup time before has deassertion (hmux=1) 2.31 ? 2.1 ? 1.93 ? 1.76 ? ns 335 address (had[0?7]) hold time after has deassertion (hmux=1) 1.65 ? 1.5 ? 1.38 ? 1.23 ? ns 336 ha[8?10] (hmux=1), ha[0?2] (hmux=0), hr/w setup time before data strobe assertion 4 read write 0 2.31 ? ? 0 2.1 ? ? 0 1.93 ? ? 0 1.76 ? ? ns ns 337 ha[8?10] (hmux=1), ha[0?2] (hmux=0), hr/w hold time after data strobe deassertion 4 1.65 ? 1.5 ? 1.38 ? 1.23 ? ns 338 delay from read data strobe deassertion to host request assertion for ?last data register? read 5, 7, 8 t c + 2.64 7.64 ? 7.19 ? 6.81 ? 6.28 ? ns 339 delay from write data strobe deassertion to host request assertion for ?last data register? write 6, 7, 8 1.5 t c + 2.64 10.14 ? 9.47 ? 8.9 ? 8.1 ? ns 340 delay from data strobe assertion to host request deassertion for ?last data register? read or write (hrod=0) 4, 7, 8 ? 12.14 ? 11.04 ? 10.12 ? 9.0 ns 341 delay from data strobe assertion to host request deassertion for ?last data register? read or write (hrod=1, open drain host request) 4, 7, 8, 9 ?300.0?300.0?300.0?300.0ns table 2-10. host interface timings 1,2,12 (continued) no. characteristic 10 expression 200 mhz 220 mhz 240 mhz 275 mhz uni t min max min max min max min max
dsp56321 technical data, rev. 11 2-16 freescale semiconductor specifications notes: 1. see the programmer?s model section in the chapter on the hi08 in the dsp56321 reference manual . 2. in the timing diagrams below, the controls pins are drawn as active low. the pin polarity is programmable. 3. this timing is applicable only if two consecutive reads from one of these registers are executed. 4. the data strobe is host read (hrd) or host write (hwr) in the dual data strobe mode and host data strobe (hds) in the single data strobe mode. 5. the read data strobe is hrd in the dual data strobe mode and hds in the single data strobe mode. 6. the write data strobe is hwr in the dual data strobe mode and hds in the single data strobe mode. 7. the host request is hreq in the single host request mode and hrrq and htrq in the double host request mode. 8. the ?last data register? is the register at address $7, which is the last location to be read or written in data transfers. thi s is rxl/txl in the big endian mode (hlend = 0; hlend is the interface control register bit 7?icr[7]), or rxh/txh in the little endian mode (hlend = 1). 9. in this calculation, the host request signal is pulled up by a 4.7 k ? resistor in the open-drain mode. 10. v ccqh = 3.3 v 0.3 v, v ccql = 1.6 v 0.1 v; t j = ?40c to +100 c, c l = 50 pf 11. this timing is applicable only if a read from the ?last data register? is followed by a read from the rxl, rxm, or rxh register s without first polling rxdf or hreq bits, or waiting for the assertion of the hreq signal. 12. after the external host writes a new value to the icr, the hi08 will be ready for operation after three dsp clock cycles (3 tc). figure 2-13. host interrupt vector register (ivr) read timing diagram table 2-10. host interface timings 1,2,12 (continued) no. characteristic 10 expression 200 mhz 220 mhz 240 mhz 275 mhz uni t min max min max min max min max hack h[0?7] hreq 329 317 318 328 326 327
ac electrical characteristics dsp56321 technical data, rev. 11 freescale semiconductor 2-17 figure 2-14. read timing diagram, non-multiplexed bus, single data strobe figure 2-15. read timing diagram, non-multiplexed bus, double data strobe hds ha[2?0] hcs h[7?0] 327 332 319 318 317 330 329 337 336 328 326 338 341 340 333 hreq (single host request) hrw 336 337 hrrq (double host request) hrd ha[2?0] hcs h[7?0] 327 332 319 318 317 330 329 337 336 328 326 338 341 340 333 hreq (single host request) hrrq (double host request)
dsp56321 technical data, rev. 11 2-18 freescale semiconductor specifications figure 2-16. write timing diagram, non-multiplexed bus, single data strobe figure 2-17. write timing diagram, non-multiplexed bus, double data strobe hds ha[2?0] hcs h[7?0] 324 321 320 331 337 336 339 341 340 333 hreq (single host request) hrw 336 337 htrq (double host request) 325 hwr ha[2?0] hcs h[7?0] 324 321 320 331 325 337 336 339 341 340 333 hreq (single host request) htrq (double host request)
ac electrical characteristics dsp56321 technical data, rev. 11 freescale semiconductor 2-19 , figure 2-18. read timing diagram, multiplexed bus, single data strobe figure 2-19. read timing diagram, multiplexed bus, double data strobe hds ha[10?8] has had[7?0] hreq (single host request) address data 317 318 319 328 329 327 326 335 336 337 334 341 340 338 323 322 hrrq (double host request) hrw 336 337 hrd ha[10?8] has had[7?0] address data 317 318 319 328 329 327 326 335 336 337 334 341 340 338 323 322 hreq (single host request) hrrq (double host request)
dsp56321 technical data, rev. 11 2-20 freescale semiconductor specifications , figure 2-20. write timing diagram, multiplexed bus, single data strobe figure 2-21. write timing diagram, multiplexed bus, double data strobe hds ha[10?8] hreq (single host request) has had[7?0] address data 320 321 325 324 335 341 339 336 334 340 322 323 hrw 336 337 htrq (double host request) 337 hwr ha[10?8] has had[7?0] address data 320 321 325 324 335 341 339 336 334 340 322 323 hreq (single host request) htrq (double host request) 337
ac electrical characteristics dsp56321 technical data, rev. 11 freescale semiconductor 2-21 2.4.7 sci timing table 2-11. sci timings no. characteristics 1 symbol expression 200 mhz 220 mhz 240 mhz 275 mhz uni t min max min max min max min max 400 synchronous clock cycle t scc 2 16 t c 80.0 ? 72.8 ? 66.7 ? 58.0 ? ns 401 clock low period t scc /2 ? 10.0 30.0 ? 26.4 ? 23.4 ? 19.0 ? ns 402 clock high period t scc /2 ? 10.0 30.0 ? 26.4 ? 23.4 ? 19.0 ? ns 403 output data setup to clock falling edge (internal clock) t scc /4 + 0.5 t c ? 17.0 5.5 ? 3.5 ? 1.76 ? ?0.68 ? ns 404 output data hold after clock rising edge (internal clock) t scc /4 ? 1.5 t c 13 ? 11.5 ? 10 ? 9.04 ? ns 405 input data setup time before clock rising edge (internal clock) t scc /4 + 0.5 t c + 25.0 47.5 ? 45.5 ? 43.8 ? 41.32 ? ns 406 input data not valid before clock rising edge (internal clock) t scc /4 + 0.5 t c ? 5.5 ? 17.0 ? 15.0 ? 13.8 ? 10.81 ns 407 clock falling edge to output data valid (external clock) ? 32.0 ? 32.0 ? 32.0 ? 32.0 ns 408 output data hold after clock rising edge (external clock) t c + 8.0 13.0 ? 12.6 ? 12.2 ? 11.64 ? ns 409 input data setup time before clock rising edge (external clock) 0.0 ? 0.0 ? 0.0 ? 0.0 ? ns 410 input data hold time after clock rising edge (external clock) 9.0 ? 9.0 ? 9.0 ? 9.0 ? ns 411 asynchronous clock cycle t acc 3 64 t c 320.0 ? 291.2 ? 266.9 ? 232.0 ? ns 412 clock low period t acc /2 ? 10.0 150.0 ? 135.6 ? 123.5 ? 106.0 ? ns 413 clock high period t acc /2 ? 10.0 150.0 ? 135.6 ? 123.5 ? 106.0 ? ns 414 output data setup to clock rising edge (internal clock) t acc /2 ? 30.0 130.0 ? 115.6 ? 103.5 ? 86.0 ? ns 415 output data hold after clock rising edge (internal clock) t acc /2 ? 30.0 130.0 ? 115.6 ? 103.5 ? 86.0 ? ns notes: 1. v ccqh = 3.3 v 0.3 v, v ccql = 1.6 v 0.1 v; t j = ?40c to +100 c, c l = 50 pf. 2. t scc = synchronous clock cycle time (for internal clock, t scc is determined by the sci clock control register and t c ). 3. t acc = asynchronous clock cycle time; value given for 1x clock mode (for internal clock, t acc is determined by the sci clock control register and t c ). 4. in the timing diagrams that follow, the sclk is drawn using the clock falling edge as a the first reference. clock polarity is programmable in the sci control register (scr). refer to the dsp56321 reference manual for details.
dsp56321 technical data, rev. 11 2-22 freescale semiconductor specifications figure 2-22. sci synchronous mode timing figure 2-23. sci asynchronous mode timing a) internal clock data valid data valid b) external clock data valid sclk (output) txd rxd sclk (input) txd rxd data valid 400 402 404 401 403 405 406 400 402 401 407 409 410 408 1x sclk (output) txd data valid 413 411 412 414 415
ac electrical characteristics dsp56321 technical data, rev. 11 freescale semiconductor 2-23 2.4.8 essi0/essi1 timing table 2-12. essi timings no. characteristics 4, 6 symbol expression 200 mhz 220 mhz 240 mhz 275 mhz cond- ition 5 unit min max min max min max min max 430 clock cycle 1 t eccx t ecci 6 t c 8 t c 30.0 40.0 ? ? 27.3 36.6 ? ? 25.0 33.3 ? ? 21.5 25.0 ? ? x ck i ck ns ns 431 clock high period for internal clock for external clock t eccx /2 ? 3.7 t ecci /2 ? 10.0 11.3 10.0 ? ? 9.9 8.2 ? ? 8.8 6.7 ? ? 7.21 2.5 ? ? ns ns 432 clock low period for internal clock for external clock t eccx /2 ? 3.7 t ecci /2 ? 10.0 11.3 10.0 ? ? 9.9 8.2 ? ? 8.8 6.7 ? ? 7.21 2.5 ? ? ns ns 433 rxc rising edge to fsr out (bit-length) high ? ? 12.5 8.3 ? ? 12.5 8.3 ? ? 12.5 8.3 ? ? 12.5 8.3 x ck i ck a ns 434 rxc rising edge to fsr out (bit-length) low ? ? 12.5 8.3 ? ? 12.5 8.3 ? ? 12.5 8.3 ? ? 12.5 8.3 x ck i ck a ns 435 rxc rising edge to fsr out (word- length-relative) high 2 ? ? 12.5 8.3 ? ? 12.5 8.3 ? ? 12.5 8.3 ? ? 12.5 8.3 x ck i ck a ns 436 rxc rising edge to fsr out (word- length-relative) low 2 ? ? 12.5 8.3 ? ? 12.5 8.3 ? ? 12.5 8.3 ? ? 12.5 8.3 x ck i ck a ns 437 rxc rising edge to fsr out (word- length) high ? ? 12.5 8.3 ? ? 12.5 8.3 ? ? 12.5 8.3 ? ? 12.5 8.3 x ck i ck a ns 438 rxc rising edge to fsr out (word- length) low ? ? 12.5 8.3 ? ? 12.5 8.3 ? ? 12.5 8.3 ? ? 12.5 8.3 x ck i ck a ns 439 data in setup time before rxc (sck in synchronous mode) falling edge 5.0 10.0 ? ? 5.0 10.0 ? ? 5.0 10.0 ? ? 5.0 10.0 ? ? x ck i ck ns 440 data in hold time after rxc falling edge 3.8 5.0 ? ? 3.8 5.0 ? ? 3.8 5.0 ? ? 3.8 5.0 ? ? x ck i ck ns 441 fsr input (bl, wr) high before rxc falling edge 2 5.0 10.0 ? ? 5.0 10.0 ? ? 5.0 10.0 ? ? 5.0 10.0 ? ? x ck i ck a ns 442 fsr input (wl) high before rxc falling edge 5.0 10.0 ? ? 5.0 10.0 ? ? 5.0 10.0 ? ? 5.0 10.0 ? ? x ck i ck a ns 443 fsr input hold time after rxc falling edge 3.8 5.0 ? ? 3.8 5.0 ? ? 3.8 5.0 ? ? 3.8 5.0 ? ? x ck i ck a ns 444 flags input setup before rxc falling edge 5.0 10.0 ? ? 5.0 10.0 ? ? 5.0 10.0 ? ? 5.0 10.0 ? ? x ck i ck s ns 445 flags input hold time after rxc falling edge 3.8 5.0 ? ? 3.8 5.0 ? ? 3.8 5.0 ? ? 3.8 5.0 ? ? x ck i ck s ns 446 txc rising edge to fst out (bit-length) high ? ? 12.5 8.3 ? ? 12.5 8.3 ? ? 12.5 8.3 ? ? 12.5 8.3 x ck i ck ns 447 txc rising edge to fst out (bit-length) low ? ? 12.5 8.3 ? ? 12.5 8.3 ? ? 12.5 8.3 ? ? 12.5 8.3 x ck i ck ns 448 txc rising edge to fst out (word- length-relative) high 2 ? ? 12.5 8.3 ? ? 12.5 8.3 ? ? 12.5 8.3 ? ? 12.5 8.3 x ck i ck ns 449 txc rising edge to fst out (word- length-relative) low 2 ? ? 12.5 8.3 ? ? 12.5 8.3 ? ? 12.5 8.3 ? ? 12.5 8.3 x ck i ck ns 450 txc rising edge to fst out (word- length) high ? ? 12.5 8.3 ? ? 12.5 8.3 ? ? 12.5 8.3 ? ? 12.5 8.3 x ck i ck ns
dsp56321 technical data, rev. 11 2-24 freescale semiconductor specifications 451 txc rising edge to fst out (word- length) low ? ? 12.5 8.3 ? ? 12.5 8.3 ? ? 12.5 8.3 ? ? 12.5 8.3 x ck i ck ns 452 txc rising edge to data out enable from high impedance ? ? 12.5 8.3 ? ? 12.5 8.3 ? ? 12.5 8.3 ? ? 12.5 8.3 x ck i ck ns 453 txc rising edge to transmitter 0 drive enable assertion ? ? 12.5 13.5 ? ? 12.5 13.5 ? ? 12.5 13.5 ? ? 12.5 13.5 x ck i ck ns 454 txc rising edge to data out valid ? ? 12.5 8.3 ? ? 12.5 8.3 ? ? 12.5 8.3 ? ? 12.5 8.3 x ck i ck ns 455 txc rising edge to data out high impedance 3 ? ? 30.0 8.3 ? ? 30.0 8.3 ? ? 30.0 8.3 ? ? 30.0 8.3 x ck i ck ns 456 txc rising edge to transmitter 0 drive enable deassertion 3 ? ? 12.5 8.3 ? ? 12.5 8.3 ? ? 12.5 8.3 ? ? 12.5 8.3 x ck i ck ns 457 fst input (bl, wr) setup time before txc falling edge 2 5.0 10.0 ? ? 5.0 10.0 ? ? 5.0 10.0 ? ? 5.0 10.0 ? ? x ck i ck ns 458 fst input (wl) to data out enable from high impedance ? ? 15.0 8.0 ? ? 15.0 8.0 ? ? 15.0 8.0 ? ? 15.0 8.0 x ck i ck ns 459 fst input (wl) to transmitter 0 drive enable assertion ? ? 15.0 18.0 ? ? 15.0 18.0 ? ? 15.0 18.0 ? ? 15.0 18.0 x ck i ck ns 460 fst input (wl) setup time before txc falling edge 5.0 10.0 ? ? 5.0 10.0 ? ? 5.0 10.0 ? ? 5.0 10.0 ? ? x ck i ck ns 461 fst input hold time after txc falling edge 3.8 5.0 ? ? 3.8 5.0 ? ? 3.8 5.0 ? ? 3.8 5.0 ? ? x ck i ck ns 462 flag output valid after txc rising edge ? ? 12.5 8.3 ? ? 12.5 8.3 ? ? 12.5 8.3 ? ? 12.5 8.3 x ck i ck ns notes: 1. for the internal clock, the external clock cycle is defined by the instruction cycle time (timing 7 in table 2-5 on page 2-4) and the essi control register. t eccx must be t c 3, in accordance with the note below table 7-1 in the dsp56321 reference manual . t ecci must be t c 4, in accordance with the explanation of cra[psr] and the essi clock generator functional block diagram shown in figure 7-3 of the dsp56321 reference manual . 2. the word-length-relative frame sync signal waveform operates the same way as the bit-length frame sync signal waveform, but spreads from one serial clock before the first bit clock (same as the bit length frame sync signal) until the one before last b it clock of the first word in the frame. 3. periodically sampled and not 100 percent tested 4. v ccqh = 3.3 v 0.3 v, v ccql = 1.6 v 0.1 v; t j = 0c to +85c, c l = 50 pf 5. txc (sck pin) = transmit clock rxc (sc0 or sck pin) = receive clock fst (sc2 pin) = transmit frame sync fsr (sc1 or sc2 pin) receive frame sync 6. i ck = internal clock; x ck = external clock i ck a = internal clock, asynchronous mode (asynchronous implies that txc and rxc are two different clocks) i ck s = internal clock, synchronous mode (synchronous implies that txc and rxc are the same clock) 7. in the timing diagrams below, the clocks and frame sync signals are drawn using the clock falling edge as a the first reference . clock and frame sync polarities are programmable in control register b (crb). refer to the dsp56321 reference manual for details. table 2-12. essi timings (continued) no. characteristics 4, 6 symbol expression 200 mhz 220 mhz 240 mhz 275 mhz cond- ition 5 unit min max min max min max min max
ac electrical characteristics dsp56321 technical data, rev. 11 freescale semiconductor 2-25 figure 2-24. essi transmitter timing last bit see note note: in network mode, output flag transitions can occur at the start of each time slot within the frame. in normal mode, the output flag state is asserted for the entire frame period. first bit 430 432 446 447 450 451 455 454 454 452 459 456 453 461 457 458 460 461 462 431 txc (input/ output) fst (bit) out fst (word) out data out transmitter 0 drive enable fst (bit) in fst (word) in flags out
dsp56321 technical data, rev. 11 2-26 freescale semiconductor specifications 2.4.9 timer timing figure 2-25. essi receiver timing table 2-13. timer timings no. characteristics expression 200 mhz 220 mhz 240 mhz 240 mhz unit min max min max min max min max 480 tio low 2 t c + 2.0 12.0 ? 11.1 ? 10.3 ? 9.27 ? ns 481 tio high 2 t c + 2.0 12.0 ? 11.1 ? 10.3 ? 9.27 ? ns 486 synchronous delay time from timer input rising edge to the external memory address out valid caused by the first interrupt instruction execution 10.25 t c + 10.0 61.2 5 ?56.6 4 ?52.7 4 ?47.2 7 ?ns notes: 1. v ccqh = 3.3 v 0.3 v, v ccql = 1.6 v 0.1 v; t j = ?40c to +100 c, c l = 50 pf 2. the maximum frequency of pulses generated by a timer will be defined after device characterization is completed. 3. in the timing diagrams below, tio is drawn using the rising edge as the reference. tio polarity is programmable in the timer control/status register (tcsr). refer to the dsp56321 reference manual for details. last bit first bit 430 432 433 437 438 440 439 443 441 442 443 445 444 431 434 rxc (input/ output) fsr (bit) out fsr (word) out data in fsr (bit) in fsr (word) in flags in
ac electrical characteristics dsp56321 technical data, rev. 11 freescale semiconductor 2-27 2.4.10 considerations for gpio use the following considerations can be helpful when gpio is used. 2.4.10.1 gpio as output the time from fetch of the instruction that changes the gpio pin to the actual change is seven core clock cycles, if the instruction is a on e -cycle instruction and there are no pipeline stalls or any other pipeline delays. the maximum rise or fall time of a gpio pin is 13 ns (ttl levels, assuming that the maximum of 50 pf load limit is met). 2.4.10.2 gpio as input gpio inputs are not synchronized with the core clock. when only one gpio bit is polled, this lack of synchronization presents no problem, since the read value can be either the previous value or the new value of the corresponding gpio pin. however, there is the risk of reading an intermediate state if: two or more gpio bits are treated as a coupled group (for example, four possible status states encoded in two bits). the read operation occurs during a simultaneous change of gpio pins (for example, the change of 00 to 11 may happen through an intermediate state of 01 or 10). therefore, when gpio bits are read, the recommended practice is to poll continuously until two consecutive read operations have identical results. figure 2-26. tio timer event input restrictions figure 2-27. timer interrupt generation tio 481 480 tio (input) first interrupt instruction execution address 486
dsp56321 technical data, rev. 11 2-28 freescale semiconductor specifications 2.4.11 jtag timing table 2-14. jtag timing no. characteristics all frequencies unit min max 500 tck frequency of operation (1/(t c 3); absolute maximum 22 mhz) 0.0 22.0 mhz 501 tck cycle time in crystal mode 45.0 ? ns 502 tck clock pulse width measured at 1.6 v 20.0 ? ns 503 tck rise and fall times 0.0 3.0 ns 504 boundary scan input data setup time 5.0 ? ns 505 boundary scan input data hold time 24.0 ? ns 506 tck low to output data valid 0.0 40.0 ns 507 tck low to output high impedance 0.0 40.0 ns 508 tms, tdi data setup time 5.0 ? ns 509 tms, tdi data hold time 25.0 ? ns 510 tck low to tdo data valid 0.0 44.0 ns 511 tck low to tdo high impedance 0.0 44.0 ns 512 trst assert time 100.0 ? ns 513 trst setup time to tck low 40.0 ? ns notes: 1. v ccqh = 3.3 v 0.3 v, v ccql = 1.6 v 0.1 v; t j = ?40c to +100 c, c l = 50 pf. 2. all timings apply to once module data transfers because it uses the jtag port as an interface. figure 2-28. test clock input timing diagram tck (input) v m v m v ih v il 501 502 502 503 503
ac electrical characteristics dsp56321 technical data, rev. 11 freescale semiconductor 2-29 figure 2-29. boundary scan (jtag) timing diagram figure 2-30. test access port timing diagram figure 2-31. trst timing diagram tck (input) data inputs data outputs data outputs data outputs v ih v il input data valid output data valid output data valid 505 504 506 507 506 tck (input) tdi (input) tdo (output) tdo (output) tdo (output) v ih v il input data valid output data valid output data valid tms 508 509 510 511 510 tck (input) trst (input) 513 512
dsp56321 technical data, rev. 11 2-30 freescale semiconductor specifications 2.4.12 once module timing table 2-15. once module timing no. characteristics expression all frequencies unit min max 500 tck frequency of operation (1/(t c 3); maximum 22 mhz) max 22.0 mhz 0.0 22.0 mhz 514 de assertion time in order to enter debug mode 1.5 t c + 10.0 20.0 ? ns 515 response time when dsp56321 is executing nop instructions from internal memory 5.5 t c + 30.0 ? 67.0 ns 516 debug acknowledge assertion time 3 t c + 5.0 25.0 ? ns note: v ccqh = 3.3 v 0.3 v, v ccql = 1.6 v 0.1 v; t j = ?40c to +100 c, c l = 50 pf figure 2-32. once?debug request de 516 515 514
dsp56321 technical data, rev. 11 freescale semiconductor 3-1 packaging 3 this section includes diagrams of the dsp56321 package pin-outs and tables showing how the signals described in chapter 1 are allocated for the package. the dsp56321 is available in a 196-pin molded array plastic-ball grid array (map-bga) package.
dsp56321 technical data, rev. 11 3-2 freescale semiconductor packaging 3.1 package description top and bottom views of the map-bga packages are shown in figure 3-1 and figure 3-2 with their pin-outs. figure 3-1. dsp56321 map-bga package, top view top view 134 2567810 14 13 12 11 9 v ccqh hack hreq b c d e f g h n m l j k ha0 hrw hds hcs irqd h5 nc h7 ha1 ha2 h2 v ccd v ccql irqa d19 d18 v ccd v ccd v ccql v ccs v ccqh gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd v cca v ccc v cca v cca v ccql v cch v ccs v ccql gnd gnd gnd gnd gnd gnd v ccd v ccqh irqc h4 h6 v ccql d12 d11 d15 d9 d5 d3 d0 a0 a17 a16 a1 a2 h1 h0 h3 tio1 rxd tio2 tio0 sck1 txd sc12 sc11 std1 sck0 srd0 srd1 std0 sc02 sc01 tdo tms de ta tdi tck a15 a12 a7 a5 bg gnd pinit aa0 trst sclk v ccc p a irqb d23 d22 d21 d20 d17 d16 d14 d13 d10 d8 d7 d6 d4 d2 d1 a14 a13 a11 a10 a9 a8 a6 a4 a3 aa1 rd wr bb br res?d xtal nc aa3 aa2 gnd nc reset sc00 sc10 nc nc nc nc gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd extal nc res?d
package description dsp56321 technical data, rev. 11 freescale semiconductor 3-3 figure 3-2. dsp56321 map-bga package, bottom view 1 3 42 5 6 7 8 10 14 13 12 11 9 v ccqh hack hreq b c d e f g h n m l j k ha0 hrw hds hcs irqd h5 nc h7 ha1 ha2 h2 v ccd v ccql irqa d19 d18 v ccd v ccd v ccql v ccs v ccqh gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd v cca v ccc v cca v cca v ccql v cch v ccs v ccql gnd gnd gnd gnd gnd gnd v ccd v ccqh irqc h4 h6 v ccql d12 d11 d15 d9 d5 d3 d0 a0 a17 a16 a1 a2 h1 h0 h3 tio1 rxd tio2 tio0 sck1 txd sc12 sc11 std1 sck0 srd0 srd1 std0 sc02 sc01 tdo tms de ta tdi tck a15 a12 a7 a5 bg gnd pinit aa0 trst sclk v ccc p a irqb d23 d22 d21 d20 d17 d16 d14 d13 d10 d8 d7 d6 d4 d2 d1 a14 a13 a11 a10 a9 a8 a6 a4 a3 aa1 rd wr bb br xtal nc aa3 aa2 gnd nc reset sc00 sc10 nc nc nc nc gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd extal bottom view res?d nc res?d
dsp56321 technical data, rev. 11 3-4 freescale semiconductor packaging table 3-1. signal list by ball number ball no. signal name ball no. signal name ball no. signal name a1 not connected (nc) b12 d8 d9 gnd a2 sc11 or pd1 b13 d5 d10 gnd a3 tms b14 nc d11 gnd a4 tdo c1 sc02 or pc2 d12 d1 a5 modb/irqb c2 std1 or pd5 d13 d2 a6 d23 c3 tck d14 v ccd a7 v ccd c4 moda/irqa e1 std0 or pc5 a8 d19 c5 modc/irqc e2 v ccs a9 d16 c6 d22 e3 srd0 or pc4 a10 d14 c7 v ccql e4 gnd a11 d11 c8 d18 e5 gnd a12 d9 c9 v ccd e6 gnd a13 d7 c10 d12 e7 gnd a14 nc c11 v ccd e8 gnd b1 srd1 or pd4 c12 d6 e9 gnd b2 sc12 or pd2 c13 d3 e10 gnd b3 tdi c14 d4 e11 gnd b4 trst d1 pinit/nmi e12 a17 b5 modd/irqd d2 sc01 or pc1 e13 a16 b6 d21 d3 de e14 d0 b7 d20 d4 gnd f1 rxd or pe0 b8 d17 d5 gnd f2 sc10 or pd0 b9 d15 d6 gnd f3 sc00 or pc0 b10 d13 d7 gnd f4 gnd b11 d10 d8 gnd f5 gnd
package description dsp56321 technical data, rev. 11 freescale semiconductor 3-5 f6 gnd h3 sck0 or pc3 j14 a9 f7 gnd h4 gnd k1 v ccs f8 gnd h5 gnd k2 hreq /hreq, htrq /htrq, or pb14 f9 gnd h6 gnd k3 tio2 f10 gnd h7 gnd k4 gnd f11 gnd h8 gnd k5 gnd f12 v ccqh h9 gnd k6 gnd f13 a14 h10 gnd k7 gnd f14 a15 h11 gnd k8 gnd g1 sck1 or pd3 h12 v cca k9 gnd g2 sclk or pe2 h13 a10 k10 gnd g3 txd or pe1 h14 a11 k11 gnd g4 gnd j1 hack /hack, hrrq /hrrq, or pb15 k12 v cca g5 gnd j2 hrw, hrd /hrd, or pb11 k13 a5 g6 gnd j3 hds /hds, hwr /hwr, or pb12 k14 a6 g7 gnd j4 gnd l1 hcs /hcs, ha10, or pb13 g8 gnd j5 gnd l2 tio1 g9 gnd j6 gnd l3 tio0 g10 gnd j7 gnd l4 gnd g11 gnd j8 gnd l5 gnd g12 a13 j9 gnd l6 gnd g13 v ccql j10 gnd l7 gnd g14 a12 j11 gnd l8 gnd h1 v ccqh j12 a8 l9 gnd h2 v ccql j13 a7 l10 gnd table 3-1. signal list by ball number (continued) ball no. signal name ball no. signal name ball no. signal name
dsp56321 technical data, rev. 11 3-6 freescale semiconductor packaging l11 gnd m13 a1 p1 nc l12 v cca m14 a2 p2 h5, had5, or pb5 l13 a3 n1 h6, had6, or pb6 p3 h3, had3, or pb3 l14 a4 n2 h7, had7, or pb7 p4 h1, had1, or pb1 m1 ha1, ha8, or pb9 n3 h4, had4, or pb4 p5 nc m2 ha2, ha9, or pb10 n4 h2, had2, or pb2 p6 gnd m3 ha0, has /has, or pb8 n5 reset p7 aa2 m4 v cch n6 gnd p8 xtal m5 h0, had0, or pb0 n7 aa3 p9 v ccc m6 v ccql n8 nc p10 ta m7 v ccqh n9 v ccql p11 bb m8 extal n10 reserved p12 aa1 m9 reserved n11 br p13 bg m10 nc n12 v ccc p14 nc m11 wr n13 aa0 m12 rd n14 a0 note: signal names are based on configured functionality. most connections supply a single signal. some connections provide a signal with dual functionality, such as the modx/irqx pins that select an operating mode after reset is deasserted but act as interrupt lines during operation. some signals have configurable polarity; these names are shown with and without overbars, such as has /has. some connections have two or more configurable functions; names assigned to these connections indicate the function for a specific configuration. for example, connection n2 is data line h7 in non-multiplexed bus mode, data/address line had7 in multiplexed bus mode, or gpio line pb7 when the gpio function is enabled for this pin. unlike the tqfp package, most of the gnd pins are connected internally in the center of the connection array and act as heat sink for the chip. table 3-1. signal list by ball number (continued) ball no. signal name ball no. signal name ball no. signal name
package description dsp56321 technical data, rev. 11 freescale semiconductor 3-7 table 3-2. signal list by signal name signal name ball no. signal name ball no. signal name ball no. a0 n14 br n11 d9 a12 a1 m13 d0 e14 de d3 a10 h13 d1 d12 extal m8 a11h14d10b11gndd4 a12 g14 d11 a11 gnd d5 a13g12d12c10gndd6 a14 f13 d13 b10 gnd d7 a15 f14 d14 a10 gnd d8 a16 e13 d15 b9 gnd d9 a17 e12 d16 a9 gnd d10 a2 m14 d17 b8 gnd d11 a3 l13 d18 c8 gnd e4 a4 l14 d19 a8 gnd e5 a5 k13 d2 d13 gnd e6 a6 k14 d20 b7 gnd e7 a7 j13 d21 b6 gnd e8 a8 j12 d22 c6 gnd e9 a9 j14 d23 a6 gnd e10 aa0n13d3c13gnde11 aa1 p12 d4 c14 gnd f4 aa2 p7 d5 b13 gnd f5 aa3 n7 d6 c12 gnd f6 bb p11d7a13gndf7 bg p13d8b12gndf8
dsp56321 technical data, rev. 11 3-8 freescale semiconductor packaging gnd f9 gnd k4 ha1 m1 gnd f10 gnd k5 ha10 l1 gnd f11 gnd k6 ha2 m2 gnd g4 gnd k7 ha8 m1 gnd g5 gnd k8 ha9 m2 gnd g6 gnd k9 hack /hack j1 gnd g7 gnd k10 had0 m5 gnd g8 gnd k11 had1 p4 gnd g9 gnd l4 had2 n4 gnd g10 gnd l5 had3 p3 gnd g11 gnd l6 had4 n3 gnd h4 gnd l7 had5 p2 gnd h5 gnd l8 had6 n1 gnd h6 gnd l9 had7 n2 gnd h7 gnd l10 has /has m3 gnd h8 gnd l11 hcs /hcs l1 gnd h9 gnd n6 hds /hds j3 gnd h10 gnd p6 hrd /hrd j2 gnd h11 h0 m5 hreq /hreq k2 gnd j4 h1 p4 hrrq /hrrq j1 gnd j5 h2 n4 hrw j2 gnd j6 h3 p3 htrq /htrq k2 gnd j7 h4 n3 hwr /hwr j3 gnd j8 h5 p2 irqa c4 gnd j9 h6 n2 irqb a5 gnd j10 h7 n2 irqc c5 gnd j11 ha0 m3 irqd b5 table 3-2. signal list by signal name (continued) signal name ball no. signal name ball no. signal name ball no.
package description dsp56321 technical data, rev. 11 freescale semiconductor 3-9 moda c4 pb4 n3 reserved m9 modb a5 pb5 p2 reserved n10 modc c5 pb6 n1 reset n5 modd b5 pb7 n2 rxd f1 nc a1 pb8 m3 sc00 f3 nc a14 pb9 m1 sc01 d2 nc b14 pc0 f3 sc02 c1 nc m10 pc1 d2 sc10 f2 nc n8 pc2 c1 sc11 a2 nc p1 pc3 h3 sc12 b2 nc p5 pc4 e3 sck0 h3 nc p14 pc5 e1 sck1 g1 nmi d1 pd0 f2 sclk g2 pb0 m5 pd1 a2 srd0 e3 pb1 p4 pd2 b2 srd1 b1 pb10 m2 pd3 g1 std0 e1 pb11 j2 pd4 b1 std1 c2 pb12 j3 pd5 c2 ta p10 pb13 l1 pe0 f1 tck c3 pb14 k2 pe1 g3 tdi b3 pb15 j1 pe2 g2 tdo a4 pb2 n4 pinit d1 tio0 l3 pb3 p3 rd m12 tio1 l2 table 3-2. signal list by signal name (continued) signal name ball no. signal name ball no. signal name ball no.
dsp56321 technical data, rev. 11 3-10 freescale semiconductor packaging 3.2 map-bga package mechanical drawing tio2 k3 v ccc p9 v ccql c7 tms a3 v ccd a7 v ccql g13 trst b4 v ccd c9 v ccql h2 txd g3 v ccd c11 v ccql m6 v cca h12 v ccd d14 v ccql n9 v cca k12 v cch m4 v ccs e2 v cca l12 v ccqh f12 v ccs k1 v ccc n12 v ccqh h1 wr m11 v ccqh m7 xtal p8 figure 3-3. dsp56321 mechanical information, 196-pin map-bga package table 3-2. signal list by signal name (continued) signal name ball no. signal name ball no. signal name ball no.
dsp56321 technical data, rev. 11 freescale semiconductor 4-1 design considerations 4 this section describes various areas to consider when incorporating the dsp56321 device into a system design. 4.1 thermal design considerations an estimate of the chip junction temperature, t j , in c can be obtained from this equation: equation 1: where: t a = ambient temperature c r ja = package junction-to-ambient thermal resistance c/w p d = power dissipation in package historically, thermal resistance has been expressed as the sum of a junction-to-case thermal resistance and a case- to-ambient thermal resistance, as in this equation: equation 2: where: r ja = package junction-to-ambient thermal resistance c/w r jc = package junction-to-case thermal resistance c/w r ca = package case-to-ambient thermal resistance c/w r jc is device-related and cannot be influenced by the user. the user controls the thermal environment to change the case-to-ambient thermal resistance, r ca . for example, the user can change the air flow around the device, add a heat sink, change the mounting arrangement on the printed circuit board (pcb) or otherwise change the thermal dissipation capability of the area surrounding the device on a pcb. this model is most useful for ceramic packages with heat sinks; some 90 percent of the heat flow is dissipated through the case to the heat sink and out to the ambient environment. for ceramic packages, in situations where the heat flow is split between a path to the case and an alternate path through the pcb, analysis of the device thermal performance may need the additional modeling capability of a system-level thermal simulation tool. the thermal performance of plastic packages is more dependent on the temperature of the pcb to which the package is mounted. again, if the estimates obtained from r ja do not satisfactorily answer whether the thermal performance is adequate, a system-level model may be appropriate. a complicating factor is the existence of three common ways to determine the junction-to-case thermal resistance in plastic packages. to minimize temperature variation across the surface, the thermal resistance is measured from the junction to the outside surface of the package (case) closest to the chip mounting area when that surface has a proper heat sink. t j t a p d r ja () + = r ja r jc r ca + =
dsp56321 technical data, rev. 11 4-2 freescale semiconductor design considerations to define a value approximately equal to a junction-to-board thermal resistance, the thermal resistance is measured from the junction to the point at which the leads attach to the case. if the temperature of the package case (t t ) is determined by a thermocouple, thermal resistance is computed from the value obtained by the equation (t j ? t t )/p d . as noted earlier, the junction-to-case thermal resistances quoted in this data sheet are determined using the first definition. from a practical standpoint, that value is also suitable to determine the junction temperature from a case thermocouple reading in forced convection environments. in natural convection, the use of the junction-to-case thermal resistance to estimate junction temperature from a thermocouple reading on the case of the package will yield an estimate of a junction temperature slightly higher than actual temperature. hence, the new thermal metric, thermal characterization parameter or jt , has been defined to be (t j ? t t )/p d . this value gives a better estimate of the junction temperature in natural convection when the surface temperature of the package is used. remember that surface temperature readings of packages are subject to significant errors caused by inadequate attachment of the sensor to the surface and to errors caused by heat loss to the sensor. the recommended technique is to attach a 40- gauge thermocouple wire and bead to the top center of the package with thermally conductive epoxy. 4.2 electrical design considerations use the following list of recommendations to ensure correct dsp operation. provide a low-impedance path from the board power supply to each v cc pin on the dsp and from the board ground to each gnd pin. use at least four 0.01?0.1 f bypass capacitors for v ccql (core) and at least six 0.01?0.1 f bypass capacitors for the other v cc (i/o) power connections positioned as closely as possible to the four sides of the package to connect the power sources to gnd . ensure that capacitor leads and associated printed circuit traces that connect to the chip v cc and gnd pins are less than 0.5 inch per capacitor lead. use at least a four-layer pcb with two inner layers for v cc and gnd . because the dsp output signals have fast rise and fall times, pcb trace lengths should be minimal. this recommendation particularly applies to the address and data buses as well as the irqa , irqb , irqc , irqd , ta , and bg pins. maximum pcb trace lengths on the order of 6 inches are recommended. caution this device contains protective circuitry to guard against damage due to high static voltage or electrical fields. however, normal precautions are advised to avoid application of any voltages higher than maximum rated voltages to this high-impedance circuit. reliability of operation is enhanced if unused inputs are tied to an appropriate logic voltage level (for example, either gnd or v cc ).
power consumption considerations dsp56321 technical data, rev. 11 freescale semiconductor 4-3 consider all device loads as well as parasitic capacitance due to pcb traces when you calculate capacitance. this is especially critical in systems with higher capacitive loads that could create higher transient currents in the v cc and gnd circuits. all inputs must be terminated (that is, not allowed to float) by cmos levels except for the three pins with internal pull-up resistors ( trst , tms , de ). the following pins must be asserted during the power-up sequence: reset and trst . a stable extal signal should be supplied before deassertion of reset . if the v cc reaches the required level before extal is stable or other ?required reset duration? conditions are met (see table 2-7 ), the device circuitry can be in an uninitialized state that may result in significant power consumption and heat-up. designs should minimize this condition to the shortest possible duration. ensure that during power-up, and throughout the dsp56321 operation, v ccqh is always higher or equal to the v ccql voltage level. if multiple dsp devices are on the same board, check for cross-talk or excessive spikes on the supplies due to synchronous operation of the devices. the port a data bus ( d[0?23] ), hi08, essi0, essi1, sci, and timers all use internal keepers to maintain the last output value even when the internal signal is tri-stated. typically, no pull-up or pull-down resistors should be used with these signal lines. however, if the dsp is connected to a device that requires pull-up resistors (such as an mpc8260), the recommended resistor value is 10 k ? or less. if more than one dsp must be connected in parallel to the other device, the pull-up resistor value requirement changes as follows: ?2 dsps = 5 k ? (mask sets 0k91m and 1k91m)/7 k ? (mask set 0k93m) or less ?3 dsps = 3 k ? (mask sets 0k91m and 1k91m)/4 k ? (mask set 0k93m) or less ?4 dsps = 2 k ? (mask sets 0k91m and 1k91m)/3 k ? (mask set 0k93m) or less ?5 dsps = 1.5 k ? (mask sets 0k91m and 1k91m)/2 k ? (mask set 0k93m) or less ?6 dsps = 1 k ? (mask sets 0k91m and 1k91m)/1.5 k ? (mask set 0k93m) or less note: refer to eb610/d dsp56321/dsp56321t power-up sequencing guidelines for detailed information about minimizing power consumption during startup. 4.3 power consumption considerations power dissipation is a key issue in portable dsp applications. some of the factors affecting current consumption are described in this section. most of the current consumed by cmos devices is alternating current (ac), which is charging and discharging the capacitances of the pins and internal nodes. current consumption is described by this formula: equation 3: where: c = node/pin capacitance v = voltage swing f = frequency of node/pin toggle example 4-1. current consumption for a port a address pin loaded with 50 pf capacitance, operating at 3.3 v, with a 66 mhz clock, toggling at its maximum possib le rate (33 mhz), the current consumption is expressed in equation 4 . icvf =
dsp56321 technical data, rev. 11 4-4 freescale semiconductor design considerations equation 4: the maximum internal current (i cci max) value reflects the typical possible switching of the internal buses on best- case operation conditions?not necessarily a real application case. the typical internal current (i ccityp ) value reflects the average switching of the internal buses on typical operating conditions. perform the following steps for applications that require very low current consumption: 1. set the ebd bit when you are not accessing external memory. 2. minimize external memory accesses, and use internal memory accesses. 3. minimize the number of pins that are switching. 4. minimize the capacitive load on the pins. 5. connect the unused inputs to pull-up or pull-down resistors. 6. disable unused peripherals. 7. disable unused pin activity (for example, clkout , xtal ). one way to evaluate power consumption is to use a current-per-mips measurement methodology to minimize specific board effects (that is, to compensate for measured board current not caused by the dsp). a benchmark power consumption test algorithm is listed in appendix a . use the test algorithm, specific test current measurements, and the following equation to derive the current-per-mips value. equation 5: where: i typf2 = current at f2 i typf1 = current at f1 f2 = high frequency (any specified operating frequency) f1 = low frequency (any specified operating frequency lower than f2) note: f1 should be significantly less than f2. for example, f2 could be 66 mhz and f1 could be 33 mhz. the degree of difference between f1 and f2 determines the amount of precision with which the current rating can be determined for an application. 4.4 input (extal) jitter requirements the allowed jitter on the frequency of extal is 0.5 percent. if the rate of change of the frequency of extal is slow (that is, it does not jump between the minimum and maximum values in one cycle) or the frequency of the jitter is fast (that is, it does not stay at an extreme value for a long time), then the allowed jitter can be 2 percent. the phase and frequency jitter performance results are valid only if the input jitter is less than the prescribed values. i 50 10 12 ? 3.3 33 10 6 5.48 ma == mips ? i mhz ? i typf2 i typf1 ? () f2 f1 ? () ? ==
dsp56321 technical data, rev. 11 freescale semiconductor a-1 power consumption benchmark a the following benchmark program evaluates dsp56321 power use in a test situation. it enables the pll, disables the external clock, and uses repeated multiply-accumulate (mac) instructions with a set of synthetic dsp application data to emulate intensive sustained dsp operation. ;************************************************************************** ;************************************************************************** ;* * ;* checks typical power consumption * ;* * ;************************************************************************** page 200,55,0,0,0 nolist i_vec equ $000000; interrupt vectors for program debug only start equ $8000; main (external) program starting address int_prog equ $100 ; internal program memory starting address int_xdat equ $0; internal x-data memory starting address int_ydat equ $0; internal y-data memory starting address include "ioequ.asm" include "intequ.asm" list org p:start ; movep #$0243ff,x:m_bcr ; ; bcr: area 3 = 2 w.s (sram) ; default: 2w.s (sram) ; movep #$00000f,x:m_pctl ; xtal disable ; pll enable ; ; load the program ; move #int_prog,r0 move #prog_start,r1 do #(prog_end-prog_start),pload_loop move p:(r1)+,x0 move x0,p:(r0)+ nop pload_loop ; ; load the x-data ; move #int_xdat,r0 move #xdat_start,r1 do #(xdat_end-xdat_start),xload_loop move p:(r1)+,x0 move x0,x:(r0)+ xload_loop
dsp56321 technical data, rev. 11 a-2 freescale semiconductor power consumption benchmark ; ; load the y-data ; move #int_ydat,r0 move #ydat_start,r1 do #(ydat_end-ydat_start),yload_loop move p:(r1)+,x0 move x0,y:(r0)+ yload_loop ; jmp int_prog prog_start move #$0,r0 move #$0,r4 move #$3f,m0 move #$3f,m4 ; clr a clr b move #$0,x0 move #$0,x1 move #$0,y0 move #$0,y1 bset #4,omr ; ebd ; sbr dor #60,_end mac x0,y0,ax:(r0)+,x1 y:(r4)+,y1 mac x1,y1,ax:(r0)+,x0 y:(r4)+,y0 add a,b mac x0,y0,ax:(r0)+,x1 mac x1,y1,a y:(r4)+,y0 move b1,x:$ff _end bra sbr nop nop nop nop prog_end nop nop xdat_start ;orgx:0 dc $262eb9 dc $86f2fe dc $e56a5f dc $616cac dc $8ffd75 dc $9210a dc $a06d7b dc $cea798 dc $8dfbf1 dc $a063d6 dc $6c6657 dc $c2a544 dc $a3662d dc $a4e762 dc $84f0f3 dc $e6f1b0
dsp56321 technical data, rev. 11 freescale semiconductor a-3 dc $b3829 dc $8bf7ae dc $63a94f dc $ef78dc dc $242de5 dc $a3e0ba dc $ebab6b dc $8726c8 dc $ca361 dc $2f6e86 dc $a57347 dc $4be774 dc $8f349d dc $a1ed12 dc $4bfce3 dc $ea26e0 dc $cd7d99 dc $4ba85e dc $27a43f dc $a8b10c dc $d3a55 dc $25ec6a dc $2a255b dc $a5f1f8 dc $2426d1 dc $ae6536 dc $cbbc37 dc $6235a4 dc $37f0d dc $63bec2 dc $a5e4d3 dc $8ce810 dc $3ff09 dc $60e50e dc $cffb2f dc $40753c dc $8262c5 dc $ca641a dc $eb3b4b dc $2da928 dc $ab6641 dc $28a7e6 dc $4e2127 dc $482fd4 dc $7257d dc $e53c72 dc $1a8c3 dc $e27540 xdat_end ydat_start ;orgy:0 dc $5b6da dc $c3f70b dc $6a39e8 dc $81e801 dc $c666a6 dc $46f8e7 dc $aaec94 dc $24233d dc $802732 dc $2e3c83 dc $a43e00
dsp56321 technical data, rev. 11 a-4 freescale semiconductor power consumption benchmark dc $c2b639 dc $85a47e dc $abfddf dc $f3a2c dc $2d7cf5 dc $e16a8a dc $ecb8fb dc $4bed18 dc $43f371 dc $83a556 dc $e1e9d7 dc $aca2c4 dc $8135ad dc $2ce0e2 dc $8f2c73 dc $432730 dc $a87fa9 dc $4a292e dc $a63ccf dc $6ba65c dc $e06d65 dc $1aa3a dc $a1b6eb dc $48ac48 dc $ef7ae1 dc $6e3006 dc $62f6c7 dc $6064f4 dc $87e41d dc $cb2692 dc $2c3863 dc $c6bc60 dc $43a519 dc $6139de dc $adf7bf dc $4b3e8c dc $6079d5 dc $e0f5ea dc $8230db dc $a3b778 dc $2bfe51 dc $e0a6b6 dc $68ffb7 dc $28f324 dc $8f2e8d dc $667842 dc $83e053 dc $a1fd90 dc $6b2689 dc $85b68e dc $622eaf dc $6162bc dc $e4a245 ydat_end ;************************************************************************** ; ; equates for dsp56321 i/o registers and ports ; ;************************************************************************** page 132,55,0,0,0 opt mex
dsp56321 technical data, rev. 11 freescale semiconductor a-5 ioequ ident 1,0 ;------------------------------------------------------------------------ ; ; equates for i/o port programming ; ;------------------------------------------------------------------------ ; register addresses m_hdr equ $ffffc9 ; host port gpio data register m_hddr equ $ffffc8 ; host port gpio direction register m_pcrc equ $ffffbf ; port c control register m_prrc equ $ffffbe ; port c direction register m_pdrc equ $ffffbd ; port c gpio data register m_pcrd equ $ffffaf ; port d control register m_prrd equ $ffffae ; port d direction data register m_pdrd equ $ffffad ; port d gpio data register m_pcre equ $ffff9f ; port e control register m_prre equ $ffff9e ; port e direction register m_pdre equ $ffff9d ; port e data register m_ogdb equ $fffffc ; once gdb register ;------------------------------------------------------------------------ ; ; equates for host interface ; ;------------------------------------------------------------------------ ; register addresses m_hcr equ $ffffc2 ; host control register m_hsr equ $ffffc3 ; host status register m_hpcr equ $ffffc4 ; host polarity control register m_hbar equ $ffffc5 ; host base address register m_hrx equ $ffffc6 ; host receive register m_htx equ $ffffc7 ; host transmit register ; hcr bits definition m_hrie equ $0 ; host receive interrupts enable m_htie equ $1 ; host transmit interrupt enable m_hcie equ $2 ; host command interrupt enable m_hf2 equ $3 ; host flag 2 m_hf3 equ $4 ; host flag 3 ; hsr bits definition m_hrdf equ $0 ; host receive data full m_htde equ $1 ; host receive data empty m_hcp equ $2 ; host command pending m_hf0 equ $3 ; host flag 0 m_hf1 equ $4 ; host flag 1 ; hpcr bits definition m_hgen equ $0 ; host port gpio enable m_ha8en equ $1 ; host address 8 enable m_ha9en equ $2 ; host address 9 enable m_hcsen equ $3 ; host chip select enable m_hren equ $4 ; host request enable m_haen equ $5 ; host acknowledge enable m_hen equ $6 ; host enable
dsp56321 technical data, rev. 11 a-6 freescale semiconductor power consumption benchmark m_hod equ $8 ; host request open drain mode m_hdsp equ $9 ; host data strobe polarity m_hasp equ $a ; host address strobe polarity m_hmux equ $b ; host multiplexed bus select m_hd_hs equ $c ; host double/single strobe select m_hcsp equ $d ; host chip select polarity m_hrp equ $e ; host request polarity m_hap equ $f ; host acknowledge polarity ;------------------------------------------------------------------------ ; ; equates for serial communications interface (sci) ; ;------------------------------------------------------------------------ ; register addresses m_stxh equ $ffff97 ; sci transmit data register (high) m_stxm equ $ffff96 ; sci transmit data register (middle) m_stxl equ $ffff95 ; sci transmit data register (low) m_srxh equ $ffff9a ; sci receive data register (high) m_srxm equ $ffff99 ; sci receive data register (middle) m_srxl equ $ffff98 ; sci receive data register (low) m_stxa equ $ffff94 ; sci transmit address register m_scr equ $ffff9c ; sci control register m_ssr equ $ffff93 ; sci status register m_sccr equ $ffff9b ; sci clock control register ; sci control register bit flags m_wds equ $7 ; word select mask (wds0-wds3) m_wds0 equ 0 ; word select 0 m_wds1 equ 1 ; word select 1 m_wds2 equ 2 ; word select 2 m_ssftd equ 3 ; sci shift direction m_sbk equ 4 ; send break m_wake equ 5 ; wakeup mode select m_rwu equ 6 ; receiver wakeup enable m_woms equ 7 ; wired-or mode select m_scre equ 8 ; sci receiver enable m_scte equ 9 ; sci transmitter enable m_ilie equ 10 ; idle line interrupt enable m_scrie equ 11 ; sci receive interrupt enable m_sctie equ 12 ; sci transmit interrupt enable m_tmie equ 13 ; timer interrupt enable m_tir equ 14 ; timer interrupt rate m_sckp equ 15 ; sci clock polarity m_reie equ 16 ; sci error interrupt enable (reie) ; sci status register bit flags m_trne equ 0 ; transmitter empty m_tdre equ 1 ; transmit data register empty m_rdrf equ 2 ; receive data register full m_idle equ 3 ; idle line flag m_or equ 4 ; overrun error flag m_pe equ 5 ; parity error m_fe equ 6 ; framing error flag m_r8 equ 7 ; received bit 8 (r8) address ; sci clock control register
dsp56321 technical data, rev. 11 freescale semiconductor a-7 m_cd equ $fff ; clock divider mask (cd0-cd11) m_cod equ 12 ; clock out divider m_scp equ 13 ; clock prescaler m_rcm equ 14 ; receive clock mode source bit m_tcm equ 15 ; transmit clock source bit ;------------------------------------------------------------------------ ; ; equates for synchronous serial interface (ssi) ; ;------------------------------------------------------------------------ ; ; register addresses of ssi0 m_tx00 equ $ffffbc ; ssi0 transmit data register 0 m_tx01 equ $ffffbb ; ssio transmit data register 1 m_tx02 equ $ffffba ; ssio transmit data register 2 m_tsr0 equ $ffffb9 ; ssi0 time slot register m_rx0 equ $ffffb8 ; ssi0 receive data register m_ssisr0 equ $ffffb7 ; ssi0 status register m_crb0 equ $ffffb6 ; ssi0 control register b m_cra0 equ $ffffb5 ; ssi0 control register a m_tsma0 equ $ffffb4 ; ssi0 transmit slot mask register a m_tsmb0 equ $ffffb3 ; ssi0 transmit slot mask register b m_rsma0 equ $ffffb2 ; ssi0 receive slot mask register a m_rsmb0 equ $ffffb1 ; ssi0 receive slot mask register b ; register addresses of ssi1 m_tx10 equ $ffffac ; ssi1 transmit data register 0 m_tx11 equ $ffffab ; ssi1 transmit data register 1 m_tx12 equ $ffffaa ; ssi1 transmit data register 2 m_tsr1 equ $ffffa9 ; ssi1 time slot register m_rx1 equ $ffffa8 ; ssi1 receive data register m_ssisr1 equ $ffffa7 ; ssi1 status register m_crb1 equ $ffffa6 ; ssi1 control register b m_cra1 equ $ffffa5 ; ssi1 control register a m_tsma1 equ $ffffa4 ; ssi1 transmit slot mask register a m_tsmb1 equ $ffffa3 ; ssi1 transmit slot mask register b m_rsma1 equ $ffffa2 ; ssi1 receive slot mask register a m_rsmb1 equ $ffffa1 ; ssi1 receive slot mask register b ; ssi control register a bit flags m_pm equ $ff ; prescale modulus select mask (pm0-pm7) m_psr equ 11 ; prescaler range m_dc equ $1f000 ; frame rate divider control mask (dc0-dc7) m_alc equ 18 ; alignment control (alc) m_wl equ $380000 ; word length control mask (wl0-wl7) m_ssc1 equ 22 ; select sc1 as tr #0 drive enable (ssc1) ; ssi control register b bit flags m_of equ $3 ; serial output flag mask m_of0 equ 0 ; serial output flag 0 m_of1 equ 1 ; serial output flag 1 m_scd equ $1c ; serial control direction mask m_scd0 equ 2 ; serial control 0 direction m_scd1 equ 3 ; serial control 1 direction m_scd2 equ 4 ; serial control 2 direction m_sckd equ 5 ; clock source direction m_shfd equ 6 ; shift direction m_fsl equ $180 ; frame sync length mask (fsl0-fsl1) m_fsl0 equ 7 ; frame sync length 0
dsp56321 technical data, rev. 11 a-8 freescale semiconductor power consumption benchmark m_fsl1 equ 8 ; frame sync length 1 m_fsr equ 9 ; frame sync relative timing m_fsp equ 10 ; frame sync polarity m_ckp equ 11 ; clock polarity m_syn equ 12 ; sync/async control m_mod equ 13 ; ssi mode select m_sste equ $1c000 ; ssi transmit enable mask m_sste2 equ 14 ; ssi transmit #2 enable m_sste1 equ 15 ; ssi transmit #1 enable m_sste0 equ 16 ; ssi transmit #0 enable m_ssre equ 17 ; ssi receive enable m_sstie equ 18 ; ssi transmit interrupt enable m_ssrie equ 19 ; ssi receive interrupt enable m_stlie equ 20 ; ssi transmit last slot interrupt enable m_srlie equ 21 ; ssi receive last slot interrupt enable m_steie equ 22 ; ssi transmit error interrupt enable m_sreie equ 23 ; si receive error interrupt enable ; ssi status register bit flags m_if equ $3 ; serial input flag mask m_if0 equ 0 ; serial input flag 0 m_if1 equ 1 ; serial input flag 1 m_tfs equ 2 ; transmit frame sync flag m_rfs equ 3 ; receive frame sync flag m_tue equ 4 ; transmitter underrun error flag m_roe equ 5 ; receiver overrun error flag m_tde equ 6 ; transmit data register empty m_rdf equ 7 ; receive data register full ; ssi transmit slot mask register a m_sstsa equ $ffff ; ssi transmit slot bits mask a (ts0-ts15) ; ssi transmit slot mask register b m_sstsb equ $ffff ; ssi transmit slot bits mask b (ts16-ts31) ; ssi receive slot mask register a m_ssrsa equ $ffff ; ssi receive slot bits mask a (rs0-rs15) ; ssi receive slot mask register b m_ssrsb equ $ffff ; ssi receive slot bits mask b (rs16-rs31) ;------------------------------------------------------------------------ ; ; equates for exception processing ; ;------------------------------------------------------------------------ ; register addresses m_iprc equ $ffffff ; interrupt priority register core m_iprp equ $fffffe ; interrupt priority register peripheral ; interrupt priority register core (iprc) m_ial equ $7 ; irqa mode mask
dsp56321 technical data, rev. 11 freescale semiconductor a-9 m_ial0 equ 0 ; irqa mode interrupt priority level (low) m_ial1 equ 1 ; irqa mode interrupt priority level (high) m_ial2 equ 2 ; irqa mode trigger mode m_ibl equ $38 ; irqb mode mask m_ibl0 equ 3 ; irqb mode interrupt priority level (low) m_ibl1 equ 4 ; irqb mode interrupt priority level (high) m_ibl2 equ 5 ; irqb mode trigger mode m_icl equ $1c0 ; irqc mode mask m_icl0 equ 6 ; irqc mode interrupt priority level (low) m_icl1 equ 7 ; irqc mode interrupt priority level (high) m_icl2 equ 8 ; irqc mode trigger mode m_idl equ $e00 ; irqd mode mask m_idl0 equ 9 ; irqd mode interrupt priority level (low) m_idl1 equ 10 ; irqd mode interrupt priority level (high) m_idl2 equ 11 ; irqd mode trigger mode m_d0l equ $3000 ; dma0 interrupt priority level mask m_d0l0 equ 12 ; dma0 interrupt priority level (low) m_d0l1 equ 13 ; dma0 interrupt priority level (high) m_d1l equ $c000 ; dma1 interrupt priority level mask m_d1l0 equ 14 ; dma1 interrupt priority level (low) m_d1l1 equ 15 ; dma1 interrupt priority level (high) m_d2l equ $30000 ; dma2 interrupt priority level mask m_d2l0 equ 16 ; dma2 interrupt priority level (low) m_d2l1 equ 17 ; dma2 interrupt priority level (high) m_d3l equ $c0000 ; dma3 interrupt priority level mask m_d3l0 equ 18 ; dma3 interrupt priority level (low) m_d3l1 equ 19 ; dma3 interrupt priority level (high) m_d4l equ $300000 ; dma4 interrupt priority level mask m_d4l0 equ 20 ; dma4 interrupt priority level (low) m_d4l1 equ 21 ; dma4 interrupt priority level (high) m_d5l equ $c00000 ; dma5 interrupt priority level mask m_d5l0 equ 22 ; dma5 interrupt priority level (low) m_d5l1 equ 23 ; dma5 interrupt priority level (high) ; interrupt priority register peripheral (iprp) m_hpl equ $3 ; host interrupt priority level mask m_hpl0 equ 0 ; host interrupt priority level (low) m_hpl1 equ 1 ; host interrupt priority level (high) m_s0l equ $c ; ssi0 interrupt priority level mask m_s0l0 equ 2 ; ssi0 interrupt priority level (low) m_s0l1 equ 3 ; ssi0 interrupt priority level (high) m_s1l equ $30 ; ssi1 interrupt priority level mask m_s1l0 equ 4 ; ssi1 interrupt priority level (low) m_s1l1 equ 5 ; ssi1 interrupt priority level (high) m_scl equ $c0 ; sci interrupt priority level mask m_scl0 equ 6 ; sci interrupt priority level (low) m_scl1 equ 7 ; sci interrupt priority level (high) m_t0l equ $300 ; timer interrupt priority level mask m_t0l0 equ 8 ; timer interrupt priority level (low) m_t0l1 equ 9 ; timer interrupt priority level (high) ;------------------------------------------------------------------------ ; ; equates for timer ; ;------------------------------------------------------------------------ ; register addresses of timer0 m_tcsr0 equ $ffff8f ; timer 0 control/status register
dsp56321 technical data, rev. 11 a-10 freescale semiconductor power consumption benchmark m_tlr0 equ $ffff8e ; timer0 load reg m_tcpr0 equ $ffff8d ; timer0 compare register m_tcr0 equ $ffff8c ; timer0 count register ; register addresses of timer1 m_tcsr1 equ $ffff8b ; timer1 control/status register m_tlr1 equ $ffff8a ; timer1 load reg m_tcpr1 equ $ffff89 ; timer1 compare register m_tcr1 equ $ffff88 ; timer1 count register ; register addresses of timer2 m_tcsr2 equ $ffff87 ; timer2 control/status register m_tlr2 equ $ffff86 ; timer2 load reg m_tcpr2 equ $ffff85 ; timer2 compare register m_tcr2 equ $ffff84 ; timer2 count register m_tplr equ $ffff83 ; timer prescaler load register m_tpcr equ $ffff82 ; timer prescalar count register ; timer control/status register bit flags m_te equ 0 ; timer enable m_toie equ 1 ; timer overflow interrupt enable m_tcie equ 2 ; timer compare interrupt enable m_tc equ $f0 ; timer control mask (tc0-tc3) m_inv equ 8 ; inverter bit m_trm equ 9 ; timer restart mode m_dir equ 11 ; direction bit m_di equ 12 ; data input m_do equ 13 ; data output m_pce equ 15 ; prescaled clock enable m_tof equ 20 ; timer overflow flag m_tcf equ 21 ; timer compare flag ; timer prescaler register bit flags m_ps equ $600000 ; prescaler source mask m_ps0 equ 21 m_ps1 equ 22 ; timer control bits m_tc0 equ 4 ; timer control 0 m_tc1 equ 5 ; timer control 1 m_tc2 equ 6 ; timer control 2 m_tc3 equ 7 ; timer control 3 ;------------------------------------------------------------------------ ; ; equates for direct memory access (dma) ; ;------------------------------------------------------------------------ ; register addresses of dma m_dstr equ fffff4 ; dma status register m_dor0 equ $fffff3 ; dma offset register 0 m_dor1 equ $fffff2 ; dma offset register 1 m_dor2 equ $fffff1 ; dma offset register 2 m_dor3 equ $fffff0 ; dma offset register 3
dsp56321 technical data, rev. 11 freescale semiconductor a-11 ; register addresses of dma0 m_dsr0 equ $ffffef ; dma0 source address register m_ddr0 equ $ffffee ; dma0 destination address register m_dco0 equ $ffffed ; dma0 counter m_dcr0 equ $ffffec ; dma0 control register ; register addresses of dma1 m_dsr1 equ $ffffeb ; dma1 source address register m_ddr1 equ $ffffea ; dma1 destination address register m_dco1 equ $ffffe9 ; dma1 counter m_dcr1 equ $ffffe8 ; dma1 control register ; register addresses of dma2 m_dsr2 equ $ffffe7 ; dma2 source address register m_ddr2 equ $ffffe6 ; dma2 destination address register m_dco2 equ $ffffe5 ; dma2 counter m_dcr2 equ $ffffe4 ; dma2 control register ; register addresses of dma4 m_dsr3 equ $ffffe3 ; dma3 source address register m_ddr3 equ $ffffe2 ; dma3 destination address register m_dco3 equ $ffffe1 ; dma3 counter m_dcr3 equ $ffffe0 ; dma3 control register ; register addresses of dma4 m_dsr4 equ $ffffdf ; dma4 source address register m_ddr4 equ $ffffde ; dma4 destination address register m_dco4 equ $ffffdd ; dma4 counter m_dcr4 equ $ffffdc ; dma4 control register ; register addresses of dma5 m_dsr5 equ $ffffdb ; dma5 source address register m_ddr5 equ $ffffda ; dma5 destination address register m_dco5 equ $ffffd9 ; dma5 counter m_dcr5 equ $ffffd8 ; dma5 control register ; dma control register m_dss equ $3 ; dma source space mask (dss0-dss1) m_dss0 equ 0 ; dma source memory space 0 m_dss1 equ 1 ; dma source memory space 1 m_dds equ $c ; dma destination space mask (dds-dds1) m_dds0 equ 2 ; dma destination memory space 0 m_dds1 equ 3 ; dma destination memory space 1 m_dam equ $3f0 ; dma address mode mask (dam5-dam0) m_dam0 equ 4 ; dma address mode 0 m_dam1 equ 5 ; dma address mode 1 m_dam2 equ 6 ; dma address mode 2 m_dam3 equ 7 ; dma address mode 3 m_dam4 equ 8 ; dma address mode 4 m_dam5 equ 9 ; dma address mode 5 m_d3d equ 10 ; dma three dimensional mode m_drs equ $f800 ; dma request source mask (drs0-drs4) m_dcon equ 16 ; dma continuous mode m_dpr equ $60000 ; dma channel priority
dsp56321 technical data, rev. 11 a-12 freescale semiconductor power consumption benchmark m_dpr0 equ 17 ; dma channel priority level (low) m_dpr1 equ 18 ; dma channel priority level (high) m_dtm equ $380000 ; dma transfer mode mask (dtm2-dtm0) m_dtm0 equ 19 ; dma transfer mode 0 m_dtm1 equ 20 ; dma transfer mode 1 m_dtm2 equ 21 ; dma transfer mode 2 m_die equ 22 ; dma interrupt enable bit m_de equ 23 ; dma channel enable bit ; dma status register m_dtd equ $3f ; channel transfer done status mask (dtd0-dtd5) m_dtd0 equ 0 ; dma channel transfer done status 0 m_dtd1 equ 1 ; dma channel transfer done status 1 m_dtd2 equ 2 ; dma channel transfer done status 2 m_dtd3 equ 3 ; dma channel transfer done status 3 m_dtd4 equ 4 ; dma channel transfer done status 4 m_dtd5 equ 5 ; dma channel transfer done status 5 m_dact equ 8 ; dma active state m_dch equ $e00 ; dma active channel mask (dch0-dch2) m_dch0 equ 9 ; dma active channel 0 m_dch1 equ 10 ; dma active channel 1 m_dch2 equ 11 ; dma active channel 2 ;------------------------------------------------------------------------ ; ; equates for enhanced filter co-processor (efcop) ; ;------------------------------------------------------------------------ m_fdir equ $ffffb0 ; efcop data input register m_fdor equ $ffffb1 ; efcop data output register m_fkir equ $ffffb2 ; efcop k-constant register m_fcnt equ $ffffb3 ; efcop filter counter m_fcsr equ $ffffb4 ; efcop control status register m_facr equ $ffffb5 ; efcop alu control register m_fdba equ $ffffb6 ; efcop data base address m_fcba equ $ffffb7 ; efcop coefficient base address m_fdch equ $ffffb8 ; efcop decimation/channel register ;----------------------------------------------------------------------- ; ; equates for phase locked loop (pll) ; ;---------------------------------------------------------------------- ; register addresses of pll m_dmfr equ $ffffd0 m_dpsc equ $ffffd0 m_pctl equ $ffffd1 ; pll control register ; pll control register m_mfi equ $f ; multiplication factor intager bits mask (mfi0-mfi3) m_mfn equ $7f0 ; multiplication factor bits mask (mfn0-mfn6) m_mfd equ $3f800 ; multiplication factor bits mask (mfd0-mfd6) m_pdf equ $3c0000 ; predivider factor bits mask (pd0-pd3) m_cplm equ 22 ; m_mfo equ 23 ; m_cdf equ $70 ; division factor bits mask (df0-df2)
dsp56321 technical data, rev. 11 freescale semiconductor a-13 m_pcod equ 0 ; pll clock output disable bit m_pstp equ 1 ; stop processing state bit m_xtld equ 2 ; xtal disable bit m_pen equ 3 ; pll enable bit ;------------------------------------------------------------------------ ; ; equates for biu ; ;------------------------------------------------------------------------ ; register addresses of biu m_bcr equ $fffffb ; bus control register m_dcr equ $fffffa ; dram control register m_aar0 equ $fffff9 ; address attribute register 0 m_aar1 equ $fffff8 ; address attribute register 1 m_aar2 equ $fffff7 ; address attribute register 2 m_aar3 equ $fffff6 ; address attribute register 3 m_idr equ $fffff5 ; id register ; bus control register m_ba0w equ $1f ; area 0 wait control mask (ba0w0-ba0w4) m_ba1w equ $3e0 ; area 1 wait control mask (ba1w0-ba14) m_ba2w equ $1c00 ; area 2 wait control mask (ba2w0-ba2w2) m_ba3w equ $e000 ; area 3 wait control mask (ba3w0-ba3w3) m_bdfw equ $1f0000 ; default area wait control mask (bdfw0-bdfw4) m_bbs equ 21 ; bus state m_blh equ 22 ; bus lock hold m_brh equ 23 ; bus request hold ; dram control register m_bcw equ $3 ; in page wait states bits mask (bcw0-bcw1) m_brw equ $c ; out of page wait states bits mask (brw0-brw1) m_bps equ $300 ; dram page size bits mask (bps0-bps1) m_bple equ 11 ; page logic enable m_bme equ 12 ; mastership enable m_bre equ 13 ; refresh enable m_bstr equ 14 ; software triggered refresh m_brf equ $7f8000 ; refresh rate bits mask (brf0-brf7) m_brp equ 23 ; refresh prescaler ; address attribute registers m_bat equ $3 ; ext. access type and pin def. bits mask (bat0-bat1) m_baap equ 2 ; address attribute pin polarity m_bpen equ 3 ; program space enable m_bxen equ 4 ; x data space enable m_byen equ 5 ; y data space enable m_bam equ 6 ; address muxing m_bpac equ 7 ; packing enable m_bnc equ $f00 ; number of address bits to compare mask (bnc0-bnc3) m_bac equ $fff000 ; address to compare bits mask (bac0-bac11) ; control and status bits in sr m_cp equ $c00000 ; mask for core-dma priority bits in sr m_ca equ 0 ; carry m_v equ 1 ; overflow
dsp56321 technical data, rev. 11 a-14 freescale semiconductor power consumption benchmark m_z equ 2 ; zero m_n equ 3 ; negative m_u equ 4 ; unnormalized m_e equ 5 ; extension m_l equ 6 ; limit m_s equ 7 ; scaling bit m_i0 equ 8 ; interupt mask bit 0 m_i1 equ 9 ; interupt mask bit 1 m_s0 equ 10 ; scaling mode bit 0 m_s1 equ 11 ; scaling mode bit 1 m_sc equ 13 ; sixteen_bit compatibility m_dm equ 14 ; double precision multiply m_lf equ 15 ; do-loop flag m_fv equ 16 ; do-forever flag m_sa equ 17 ; sixteen-bit arithmetic m_ce equ 19 ; instruction cache enable m_sm equ 20 ; arithmetic saturation m_rm equ 21 ; rounding mode m_cp0 equ 22 ; bit 0 of priority bits in sr m_cp1 equ 23 ; bit 1 of priority bits in sr ; control and status bits in omr m_cdp equ $300; mask for core-dma priority bits in omr m_ma equ0 ; operating mode a m_mb equ1 ; operating mode b m_mc equ2 ; operating mode c m_md equ3 ; operating mode d m_ebd equ 4 ; external bus disable bit in omr m_sd equ 6 ; stop delay m_ms equ 7 ; memory switch bit in omr m_cdp0 equ 8 ; bit 0 of priority bits in omr m_cdp1 equ 9 ; bit 1 of priority bits in omr m_ben equ 10 ; burst enable m_tas equ 11 ; ta synchronize select m_brt equ 12 ; bus release timing m_ate equ 15 ; address tracing enable bit in omr. m_xys equ 16 ; stack extension space select bit in omr. m_eun equ 17 ; extensed stack underflow flag in omr. m_eov equ 18 ; extended stack overflow flag in omr. m_wrp equ 19 ; extended wrap flag in omr. m_sen equ 20 ; stack extension enable bit in omr. ;************************************************************************* ; ; equates for dsp56321 interrupts ; ;************************************************************************* page 132,55,0,0,0 opt mex intequ ident 1,0 if @def(i_vec) ;leave user definition as is. else i_vec equ $0 endif
dsp56321 technical data, rev. 11 freescale semiconductor a-15 ;------------------------------------------------------------------------ ; non-maskable interrupts ;------------------------------------------------------------------------ i_reset equ i_vec+$00 ; hardware reset i_stack equ i_vec+$02 ; stack error i_ill equ i_vec+$04 ; illegal instruction i_dbg equ i_vec+$06 ; debug request i_trap equ i_vec+$08 ; trap i_nmi equ i_vec+$0a ; non maskable interrupt ;------------------------------------------------------------------------ ; interrupt request pins ;------------------------------------------------------------------------ i_irqa equ i_vec+$10 ; irqa i_irqb equ i_vec+$12 ; irqb i_irqc equ i_vec+$14 ; irqc i_irqd equ i_vec+$16 ; irqd ;------------------------------------------------------------------------ ; dma interrupts ;------------------------------------------------------------------------ i_dma0 equ i_vec+$18 ; dma channel 0 i_dma1 equ i_vec+$1a ; dma channel 1 i_dma2 equ i_vec+$1c ; dma channel 2 i_dma3 equ i_vec+$1e ; dma channel 3 i_dma4 equ i_vec+$20 ; dma channel 4 i_dma5 equ i_vec+$22 ; dma channel 5 ;------------------------------------------------------------------------ ; timer interrupts ;------------------------------------------------------------------------ i_tim0c equ i_vec+$24 ; timer 0 compare i_tim0of equ i_vec+$26 ; timer 0 overflow i_tim1c equ i_vec+$28 ; timer 1 compare i_tim1of equ i_vec+$2a ; timer 1 overflow i_tim2c equ i_vec+$2c ; timer 2 compare i_tim2of equ i_vec+$2e ; timer 2 overflow ;------------------------------------------------------------------------ ; essi interrupts ;------------------------------------------------------------------------ i_si0rd equ i_vec+$30 ; essi0 receive data i_si0rde equ i_vec+$32 ; essi0 receive data w/ exception status i_si0rls equ i_vec+$34 ; essi0 receive last slot i_si0td equ i_vec+$36 ; essi0 transmit data i_si0tde equ i_vec+$38 ; essi0 transmit data w/ exception status i_si0tls equ i_vec+$3a ; essi0 transmit last slot i_si1rd equ i_vec+$40 ; essi1 receive data i_si1rde equ i_vec+$42 ; essi1 receive data w/ exception status i_si1rls equ i_vec+$44 ; essi1 receive last slot i_si1td equ i_vec+$46 ; essi1 transmit data i_si1tde equ i_vec+$48 ; essi1 transmit data w/ exception status i_si1tls equ i_vec+$4a ; essi1 transmit last slot ;------------------------------------------------------------------------ ; sci interrupts ;------------------------------------------------------------------------ i_scird equ i_vec+$50 ; sci receive data i_scirde equ i_vec+$52 ; sci receive data with exception status i_scitd equ i_vec+$54 ; sci transmit data i_sciil equ i_vec+$56 ; sci idle line i_scitm equ i_vec+$58 ; sci timer
dsp56321 technical data, rev. 11 a-16 freescale semiconductor power consumption benchmark ;------------------------------------------------------------------------ ; host interrupts ;------------------------------------------------------------------------ i_hrdf equ i_vec+$60 ; host receive data full i_htde equ i_vec+$62 ; host transmit data empty i_hc equ i_vec+$64 ; default host command ;----------------------------------------------------------------------- ; efcop filter interrupts ;----------------------------------------------------------------------- i_fdiie equ i_vec+$68 ; efilter input buffer empty i_fdoie equ i_vec+$6a ; efilter output buffer full ;------------------------------------------------------------------------ ; interrupt ending address ;------------------------------------------------------------------------ i_intend equ i_vec+$ff ; last address of interrupt vector space

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